Abstract: A tray for carrying a display panel is disclosed, and the tray includes a base configured to support the display panel, supporting members on the base and each having an inner surface corresponding to two adjacent sides of each of corner portions of the display panel, and buffering members coupled to the inner surface of each of the supporting members and configured to contact the two adjacent sides of the display panel, wherein the buffering members are spaced apart from the inner surface of each of the supporting members by a set distance.

Abstract: A tray for carrying a display panel is disclosed, and the tray includes a base configured to support the display panel, supporting members on the base and each having an inner surface corresponding to two adjacent sides of each of corner portions of the display panel, and buffering members coupled to the inner surface of each of the supporting members and configured to contact the two adjacent sides of the display panel, wherein the buffering members are spaced apart from the inner surface of each of the supporting members by a set distance.

Abstract: An electrostatic protection circuit may include a test pad configured to receive a first signal in a test mode. The electrostatic protection circuit may include a bump array configured to receive a second signal in a normal mode. The electrostatic protection circuit may include a buffer array configured to transmit the first signal or the second signal into a semiconductor device. The electrostatic protection circuit may include an electrostatic protection unit coupled with the test pad and the bump array, and configured to block static electricity included in the first signal and the second signal.

Abstract: An electrostatic protection circuit may include a test pad configured to receive a first signal in a test mode. The electrostatic protection circuit may include a bump array configured to receive a second signal in a normal mode. The electrostatic protection circuit may include a buffer array configured to transmit the first signal or the second signal into a semiconductor device. The electrostatic protection circuit may include an electrostatic protection unit coupled with the test pad and the bump array, and configured to block static electricity included in the first signal and the second signal.

Abstract: A substrate storage container includes a body including a bottom surface and a plurality of sidewalls extending perpendicularly from the bottom surface in a first direction to cooperatively provide an accommodating space for receiving a substrate, a first engaging portion provided in at least one sidewall of the plurality of sidewalls of the body and including a plurality of first positioning latching members which is arranged toward the accommodating space in a second direction perpendicular to the first direction, and a first positioning block detachably engaged with the first engaging portion and including a second positioning latching member which is engaged with any one of the plurality of first positioning latching members to adjust a capacity of the accommodating space corresponding to an engagement position of the second positioning latching member in the second direction.

Abstract: An integrated circuit may include a first semiconductor device and a second semiconductor device. The first semiconductor device may compare a first internal voltage signal with a reference voltage signal received from outside the first semiconductor device to control a drive of the first internal voltage signal. The second semiconductor device may compare a second internal voltage signal with the first internal voltage signal controlled by the first semiconductor device to control a drive of the second internal voltage signal.

Abstract: A substrate storage container includes a body including a bottom surface and a plurality of sidewalls extending perpendicularly from the bottom surface in a first direction to cooperatively provide an accommodating space for receiving a substrate, a first engaging portion provided in at least one sidewall of the plurality of sidewalls of the body and including a plurality of first positioning latching members which is arranged toward the accommodating space in a second direction perpendicular to the first direction, and a first positioning block detachably engaged with the first engaging portion and including a second positioning latching member which is engaged with any one of the plurality of first positioning latching members to adjust a capacity of the accommodating space corresponding to an engagement position of the second positioning latching member in the second direction.

Abstract: A multi-chip semiconductor apparatus includes a plurality of semiconductor chips electrically connected and stacked. Each of the semiconductor chips trims a voltage level used in the semiconductor chip in response to a chip select signal.

Abstract: A multi-chip semiconductor apparatus includes a plurality of semiconductor chips electrically connected and stacked. Each of the semiconductor chips trims a voltage level used in the semiconductor chip in response to a chip select signal.

Abstract: A clock signal generation circuit includes a clock delay control signal generation unit configured to divide a clock signal to generate a divided clock signal, generate a plurality of periodic signals which have different periods with each other during a half period of the divided clock signal, and output clock delay control signals from the plurality of periodic signals, and a doubler clock generation unit configured to delay the clock signal in response to the clock delay control signals to generate a delayed clock signal, and generate an output clock signal by mixing phases of the clock signal and the delayed clock signal.

Abstract: A clock signal generation circuit includes a clock delay control signal generation unit and a doubler clock generation unit. The clock delay control signal generation unit divides a clock signal to generate a divided clock signal, generates a plurality of periodic signals for a half period of the divided clock signal, and generates clock delay control signals from the plurality of periodic signals. The doubler clock generation unit delays the clock signal in response to the clock delay control signals to generate a delayed clock signal, and generates an output clock signal in response to the clock signal and the delayed clock signal.

Abstract: A delay locked loop circuit includes a phase comparison unit configured to compare a reference clock with a feedback clock and to output a phase comparison signal, a clock delay unit configured to delay a first reference clock in response to the phase comparison signal, to output a first delay locked clock, to delay one of the first delay locked clock and a second reference clock according to a frequency information signal, and to output a second delay locked clock, a delay locked clock generating unit configured to output a delay locked clock as a phase-mixed clock of the first delay locked clock and the second delay locked clock, the first delay locked clock, or the second delay locked clock in response to the frequency information signal and a delay transfer signal, and a delay replica model unit configured to reflect a delay condition of the reference clock.

Abstract: Provided is a signal amplification apparatus with advanced linearization, the signal amplification apparatus including: a driving unit having a structure of a cascode amplifier including a first active element and a second active element and outputting an amplification signal in which an input signal is amplified, to an output terminal; a third active element receiving a signal diverged between the first active element and the second active element while gate and drain terminals of the third active element are shorted; a fourth active element of which gate and drain terminals are connected to a source terminal of the third active element; and a fifth active element of which gate terminal is connected to the drain terminal of the fourth active element, outputting a non-linear signal having an opposite phase to the amplification signal to the output terminal so as to cancel a third-order inter-modulation distortion component included in the input signal.

Abstract: An apparatus for generating a reference clock for a DLL circuit includes a buffering unit configured to buffer an external clock so as to generate a first reference clock and a second reference clock, and to invert the second reference clock so as to generate a negative second reference clock. A duty cycle compensating unit generates a reference clock from the first reference clock and the negative second reference clock.

Abstract: Provided is a signal amplification apparatus with advanced linearization, the signal amplification apparatus including: a driving unit having a structure of a cascode amplifier including a first active element and a second active element and outputting an amplification signal in which an input signal is amplified, to an output terminal; a third active element receiving a signal diverged between the first active element and the second active element while gate and drain terminals of the third active element are shorted; a fourth active element of which gate and drain terminals are connected to a source terminal of the third active element; and a fifth active element of which gate terminal is connected to the drain terminal of the fourth active element, outputting a non-linear signal having an opposite phase to the amplification signal to the output terminal so as to cancel a third-order inter-modulation distortion component included in the input signal.

Abstract: A delay locked loop circuit includes a phase comparison unit configured to compare a reference clock with a feedback clock and to output a phase comparison signal, a clock delay unit configured to delay a first reference clock in response to the phase comparison signal, to output a first delay locked clock, to delay one of the first delay locked clock and a second reference clock according to a frequency information signal, and to output a second delay locked clock, a delay locked clock generating unit configured to output a delay locked clock as a phase-mixed clock of the first delay locked clock and the second delay locked clock, the first delay locked clock, or the second delay locked clock in response to the frequency information signal and a delay transfer signal, and a delay replica model unit configured to reflect a delay condition of the reference clock.

Abstract: A multi-stage amplification circuit includes a common differential amplification unit configured to receive and detect differential input signals to generate a positive signal and a negative signal, a positive signal amplification unit configured to receive the positive signal and the negative signal through differential input terminals to generate a positive amplification signal, and a negative signal amplification unit configured to receive the positive signal and the negative signal through differential input terminals to generate a negative amplification signal.

Abstract: An apparatus for generating a reference clock for a DLL circuit includes a buffering unit configured to buffer an external clock so as to generate a first reference clock and a second reference clock, and to invert the second reference clock so as to generate a negative second reference clock. A duty cycle compensating unit generates a reference clock from the first reference clock and the negative second reference clock.

Abstract: An apparatus for generating a reference clock for a DLL circuit includes a buffering unit configured to buffer an external clock so as to generate a first reference clock and a second reference clock, and to invert the second reference clock so as to generate a negative second reference clock. A duty cycle compensating unit generates a reference clock from the first reference clock and the negative second reference clock.

Abstract: An apparatus for generating a reference clock for a DLL circuit includes a buffering unit configured to buffer an external clock so as to generate a first reference clock and a second reference clock, and to invert the second reference clock so as to generate a negative second reference clock. A duty cycle compensating unit generates a reference clock from the first reference clock and the negative second reference clock.