Patents by Inventor Nam-Seok Suh
Nam-Seok Suh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9443881Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.Type: GrantFiled: October 20, 2014Date of Patent: September 13, 2016Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Jean-Ho Song, Shin-Il Choi, Sun-Young Hong, Shi-Yul Kim, Ki-Yeup Lee, Jae-Hyoung Youn, Sung-Ryul Kim, O-Sung Seo, Yang-Ho Bae, Jong-Hyun Choung, Dong-Ju Yang, Bong-Kyun Kim, Hwa-Yeul Oh, Pil-Soon Hong, Byeong-Beom Kim, Je-Hyeong Park, Yu-Gwang Jeong, Jong-In Kim, Nam-Seok Suh
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Publication number: 20150053984Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.Type: ApplicationFiled: October 20, 2014Publication date: February 26, 2015Inventors: JEAN-HO SONG, Shin-Il Choi, Sun-Young Hong, Shi-Yul Kim, Ki-Yeup Lee, Jae-Hyoung Youn, Sung-Ryul Kim, O-Sung Seo, Yang-Ho Bae, Jong-Hyun Choung, Dong-Ju Yang, Bong-Kyun Kim, Hwa-Yeul Oh, Pil-Soon Hong, Byeong-Beom Kim, Je-Hyeong Park, Yu-Gwang Jeong, Jong-In Kim, Nam-Seok Suh
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Patent number: 8865528Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.Type: GrantFiled: July 27, 2010Date of Patent: October 21, 2014Assignee: Samsung Display Co., Ltd.Inventors: Jean-Ho Song, Shin-Il Choi, Sun-Young Hong, Shi-Yul Kim, Ki-Yeup Lee, Jae-Hyoung Youn, Sung-Ryul Kim, O-Sung Seo, Yang-Ho Bae, Jong-Hyun Choung, Dong-Ju Yang, Bong-Kyun Kim, Hwa-Yeul Oh, Pil-Soon Hong, Byeong-Beom Kim, Je-Hyeong Park, Yu-Gwang Jeong, Jong-In Kim, Nam-Seok Suh
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Patent number: 8557621Abstract: A method for manufacturing a thin film transistor array panel, including: sequentially forming a first silicon layer, a second silicon layer, a lower metal layer, and an upper metal layer on a gate insulating layer and a gate line; forming a first film pattern on the upper metal layer; forming a first lower metal pattern and a first upper metal pattern that includes a protrusion, by etching the upper metal layer and the lower metal layer; forming first and second silicon patterns by etching the first and second silicon layers; forming a second film pattern by ashing the first film pattern; forming a second upper metal pattern by etching the first upper metal pattern; forming a data line and a thin film transistor by etching the first lower metal pattern and the first and second silicon patterns; and forming a passivation layer and a pixel electrode on the resultant.Type: GrantFiled: June 10, 2011Date of Patent: October 15, 2013Assignee: Samsung Display Co., Ltd.Inventors: Jong-Hyun Choung, Yang Ho Bae, Jean Ho Song, O Sung Seo, Sun-Young Hong, Hwa Yeul Oh, Bong-Kyun Kim, Nam Seok Suh, Dong-Ju Yang, Wang Woo Lee
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Patent number: 8377325Abstract: Exemplary embodiments of the present invention provide a metal wiring etchant. A metal wiring etchant according to an exemplary embodiment of the present invention includes ammonium persulfate, an organic acid, an ammonium salt, a fluorine-containing compound, a glycol-based compound, and an azole-based compound.Type: GrantFiled: February 22, 2011Date of Patent: February 19, 2013Assignee: Samsung Display Co., Ltd.Inventors: Nam-Seok Suh, Sun-Young Hong, Jong-Hyun Choung, Bong-Kyun Kim, Hong-Sick Park, Jean-Ho Song, Wang-Woo Lee, Do-Won Kim, Sang-Woo Kim, Won-Guk Seo, Hyun-Cheol Shin, Ki-Beom Lee, Sam-Young Cho
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Publication number: 20120135555Abstract: A method for manufacturing a thin film transistor array panel, including: sequentially forming a first silicon layer, a second silicon layer, a lower metal layer, and an upper metal layer on a gate insulating layer and a gate line; forming a first film pattern on the upper metal layer; forming a first lower metal pattern and a first upper metal pattern that includes a protrusion, by etching the upper metal layer and the lower metal layer; forming first and second silicon patterns by etching the first and second silicon layers; forming a second film pattern by ashing the first film pattern; forming a second upper metal pattern by etching the first upper metal pattern; forming a data line and a thin film transistor by etching the first lower metal pattern and the first and second silicon patterns; and forming a passivation layer and a pixel electrode on the resultant.Type: ApplicationFiled: June 10, 2011Publication date: May 31, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-Hyun CHOUNG, Yang Ho BAE, Jean Ho SONG, O. Sung SEO, Sun-Young HONG, Hwa Yeul OH, Bong-Kyun KIM, Nam Seok SUH, Dong-Ju YANG, Wang Woo LEE
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Patent number: 8058114Abstract: A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.Type: GrantFiled: June 9, 2010Date of Patent: November 15, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jang-Soo Kim, Hong-Long Ning, Bong-Kyun Kim, Hong-Sick Park, Shi-Yul Kim, Chang-Oh Jeong, Sang-Gab Kim, Jae-Hyoung Youn, Woo-Geun Lee, Yang-Ho Bae, Pil-Sang Yun, Jong-Hyun Choung, Sun-Young Hong, Ki-Won Kim, Byeong-Jin Lee, Young-Wook Lee, Jong-In Kim, Byeong-Beom Kim, Nam-Seok Suh
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Publication number: 20110226727Abstract: Exemplary embodiments of the present invention provide a metal wiring etchant. A metal wiring etchant according to an exemplary embodiment of the present invention includes ammonium persulfate, an organic acid, an ammonium salt, a fluorine-containing compound, a glycol-based compound, and an azole-based compound.Type: ApplicationFiled: February 22, 2011Publication date: September 22, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Nam-Seok SUH, Sun-Young HONG, Jong-Hyun CHOUNG, Bong-Kyun KIM, Hong-Sick PARK, Jean-Ho SONG, Wang-Woo LEE, Do-Won KIM, Sang-Woo KIM, Won-Guk SEO, Hyun-Cheol SHIN, Ki-Beom LEE, Sam-Young CHO
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Patent number: 7968000Abstract: An etchant composition is provided. The etchant composition includes about 40 to about 65 wt % of phosphoric acid, about 2 to about 5 wt % of nitric acid, about 2 to about 20 wt % of acetic acid, about 0.1 to about 2 wt % of a compound containing phosphate, about 0.1 to about 2 wt % of a compound simultaneously containing an amino group and a carboxyl group, and a remaining weight percent of water for the total weight of the composition.Type: GrantFiled: April 29, 2009Date of Patent: June 28, 2011Assignees: Samsung Electronics, Co., Ltd., Dongwoo Fine-Chem Co., Ltd.Inventors: Young-Joo Choi, Bong-Kyun Kim, Byeong-Jin Lee, Jong-Hyun Choung, Sun-Young Hong, Nam-Seok Suh, Hong-Sick Park, Ky-Sub Kim, Seung-Yong Lee, Joon-Woo Lee, Young-Chul Park, Young-Jun Jin, Seung-Jae Yang, Hyun-Kyu Lee, Sang-Hoon Jang, Min-Ki Lim
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Publication number: 20110133193Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.Type: ApplicationFiled: July 27, 2010Publication date: June 9, 2011Inventors: Jean-Ho SONG, Shin-Il Choi, Sun-Young Hong, Shi-Yul Kim, Ki-Yeup Lee, Jae-Hyoung Youn, Sung-Ryul Kim, O-Sung Seo, Yang-Ho Bae, Jong-Hyun Choung, Dong-Ju Yang, Bong-Kyun Kim, Hwa-Yeul Oh, Pil-Soon Hong, Byeong-Beom Kim, Je-Hyeong Park, Yu-Gwang Jeong, Jong-In Kim, Nam-Seok Suh
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Patent number: 7956393Abstract: A composition for a photoresist stripper and a method of fabricating a thin film transistor array substrate are provided according to one or more embodiments. In one or more embodiments, the composition includes about 5-30 weight % of a chain amine compound, about 0.5-10 weight % of a cyclic amine compound, about 10-80 weight % of a glycol ether compound, about 5-30 weight % of distilled water, and about 0.1-5 weight % of a corrosion inhibitor.Type: GrantFiled: September 21, 2009Date of Patent: June 7, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Hyun Choung, Bong-Kyun Kim, Hong-Sick Park, Sun-Young Hong, Young-Joo Choi, Byeong-Jin Lee, Nam-Seok Suh, Byung-Uk Kim, Suk-Il Yoon, Jong-Hyun Jeong, Sung-Gun Shin, Soon-Beom Huh, Se-Hwan Jung, Doo-Young Jang, Sun-Joo Park, Oh-Hwan Kweon
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Publication number: 20100261322Abstract: A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.Type: ApplicationFiled: June 9, 2010Publication date: October 14, 2010Inventors: Jang-Soo Kim, Hong-Long Ning, Bong-Kyun Kim, Hong-Sick Park, Shi-Yul Kim, Chang-Oh Jeong, Sang-Gab Kim, Jae-Hyoung Youn, Woo-Geun Lee, Yang-Ho Bae, Pil-Sang Yun, Jong-Hyun Choung, Sun-Young Hong, Ki-Won Kim, Byeong-Jin Lee, Young-Wook Lee, Jong-In Kim, Byeong-Beom Kim, Nam-Seok Suh
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Patent number: 7759738Abstract: A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.Type: GrantFiled: November 12, 2008Date of Patent: July 20, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jang-Soo Kim, Hong-Long Ning, Bong-Kyun Kim, Hong-Sick Park, Shi-Yul Kim, Chang-Oh Jeong, Sang-Gab Kim, Jae-Hyoung Youn, Woo-Geun Lee, Yang-Ho Bae, Pil-Sang Yun, Jong-Hyun Choung, Sun-Young Hong, Ki-Won Kim, Byeong-Jin Lee, Young-Wook Lee, Jong-In Kim, Byeong-Beom Kim, Nam-Seok Suh
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Publication number: 20100155730Abstract: In the manufacturing process of the thin film transistor array panel according to an exemplary embodiment of the present invention using three masks, the metal oxide semiconductor or the transparent conductive oxide is used, thereby executing an efficient lift-off process.Type: ApplicationFiled: June 9, 2009Publication date: June 24, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun-Young HONG, Young-Joo CHOI, Nam-Seok SUH, Hong-Sick PARK, Jong-Hyun CHOUNG, Bong-Kyun KIM, Byeong-Jin LEE
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Publication number: 20100159400Abstract: A composition for removing a photoresist pattern includes about 5 percent by weight to about 20 percent by weight of an aminoethoxy ethanol, about 2 percent by weight to about 10 percent by weight of a polyalkylene oxide, about 10 percent by weight to about 30 percent by weight of a glycol ether compound, and a remainder of an aprotic polar solvent including a nitrogen. Thus, the photoresist pattern can be easily removed from a substrate, thereby improving the removing ability of the composition. In addition, a residual amount of the photoresist pattern may be minimized, thereby improving the reliability of removing the photoresist pattern.Type: ApplicationFiled: December 2, 2009Publication date: June 24, 2010Applicants: SAMSUNG ELECTRONICS CO., LTD., ENF TECHNOLOGY CO., LTD.Inventors: Sun-Young HONG, Nam-Seok SUH, Hong-Sik PARK, Sang-Dai LEE, Young-Jin PARK, Jong-Hyun CHOUNG, Bong-Kyun KIM, Byeong-Jin LEE
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Publication number: 20100151610Abstract: A composition for a photoresist stripper and a method of fabricating a thin film transistor array substrate are provided according to one or more embodiments. In one or more embodiments, the composition includes about 5-30 weight % of a chain amine compound, about 0.5-10 weight % of a cyclic amine compound, about 10-80 weight % of a glycol ether compound, about 5-30 weight % of distilled water, and about 0.1-5 weight % of a corrosion inhibitor.Type: ApplicationFiled: September 21, 2009Publication date: June 17, 2010Inventors: Jong-Hyun CHOUNG, Bong-Kyun KIM, Hong-Sick PARK, Sun-Young HONG, Young-Joo CHOI, Byeong-Jin LEE, Nam-Seok SUH, Byung-Uk KIM, Suk-Il YOON, Jong-Hyun JEONG, Sung-Gun SHIN, Soon-Beom HUH, Se-Hwan JUNG, Doo-Young JANG, Sun-Joo PARK, Oh-Hwan KWEON
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Publication number: 20100149476Abstract: A display substrate includes; a base substrate, a deformation preventing layer disposed on a lower surface of the base substrate, wherein the deformation preventing layer applies a force to the base substrate to prevent the base substrate from bending, a gate line disposed on an upper surface of the base substrate, a data line disposed on the base substrate, and a pixel electrode disposed on the base substrate.Type: ApplicationFiled: August 3, 2009Publication date: June 17, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Do-Hyun KIM, Jong-Hyun CHOUNG, Young-Joo CHOI, Hong-Sick PARK, Tae-Hyung IHN, Dong-Hoon LEE, Pil-Sang YUN, Je-Hyeong PARK, Chang-Oh JEONG, Je-Hun LEE, Sun-Young HONG, Bong-Kyun KIM, Byeong-Jin LEE, Nam-Seok SUH
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Publication number: 20100120209Abstract: An etchant composition is provided. The etchant composition includes about 40 to about 65 wt % of phosphoric acid, about 2 to about 5 wt % of nitric acid, about 2 to about 20 wt % of acetic acid, about 0.1 to about 2 wt % of a compound containing phosphate, about 0.1 to about 2 wt % of a compound simultaneously containing an amino group and a carboxyl group, and a remaining weight percent of water for the total weight of the composition.Type: ApplicationFiled: April 29, 2009Publication date: May 13, 2010Inventors: Young-Joo CHOI, Bong-Kyun KIM, Byeong-Jin LEE, Jong-Hyun CHOUNG, Sun-Young HONG, Nam-Seok SUH, Hong-Sick PARK, Ky-Sub KIM, Seung-Yong LEE, Joon-Woo LEE, Young-Chul PARK, Young-Jun JIN, Seung-Jae YANG, Hyun-Kyu LEE, Sang-Hoon JANG, Min-Ki LIM
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Publication number: 20100051934Abstract: A thin film transistor array panel and a method of manufacturing the same are provided according to one or more embodiments.Type: ApplicationFiled: July 16, 2009Publication date: March 4, 2010Inventors: Jong-Hyun Choung, Bong-Kyun Kim, Byeong-Jin Lee, Sun-Young Hong, Pil-Sang Yun, Hong-Sick Park, Dong-Ju Yang, Young-Joo Choi, Nam-Seok Suh
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Publication number: 20090121228Abstract: A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.Type: ApplicationFiled: November 12, 2008Publication date: May 14, 2009Inventors: Jang-Soo Kim, Hong-Long Ning, Bong-Kyun Kim, Hong-Sick Park, Shi-Yul Kim, Chang-Oh Jeong, Sang-Gab Kim, Jae-Hyoung Youn, Woo-Geun Lee, Yang-Ho Bae, Pil-Sang Yun, Jong-Hyun Choung, Sun-Young Hong, Ki-Won Kim, Byeong-Jin Lee, Yopung-Wook Lee, Jong-In Kim, Byeong-Beom Kim, Nam-Seok Suh