Abstract: A power module includes an upper substrate and a lower substrate, an upper chip, a lower chip, and a circuit board disposed across a space between the upper substrate and the lower chip and a space between the lower substrate and the upper chip so that the upper substrate and the lower substrate are vertically spaced from each other. The circuit board electrically connects the upper chip to the lower substrate while electrically connecting the lower chip to the upper substrate.

Abstract: A data processing system includes: a first memory system including a first memory device and a first controller for controlling the first memory device; a second memory system including a second memory device; a first connector suitable for supporting the first memory system to be coupled with the second memory system through a first connection method; a second connector suitable for supporting the second memory system to be coupled with the first memory system through a second connection method; and a third connector that couples the first memory system and the second memory system with each other.

Abstract: Semiconductor devices are tested under actual operating conditions by interfacing the devices to an actual board-type product, for example, through a test board tat includes a mounting unit such as a socket or pattern of conductive lands that allows the devices being tested to be mounted to and removed from the test board with minimal effort and signal degradation. An interface circuit on the test board compensates for environmental differences between the board-type product and the mounting unit. For example, the interface circuit can include a clock distribution circuit, which utilizes a phase locked loop, and a register circuit to compensate for electrical loading caused by the device mounting unit, and to provide the proper timing margins between clock signals and control signals applied to the semiconductor devices. A power control circuit can be used to manipulate the supply voltage thereby providing a voltage margin screening function.

Abstract: A method and apparatus for testing semiconductor devices allows devices to be tested under actual operating conditions by interfacing the devices to an actual board-type product. The semiconductor devices are interfaced to the board-type product with a test board that includes a mounting unit such as a socket or pattern of conductive lands that allows the devices being tested can be easily mounted to and removed from the test board with minimal effort and signal degradation. An interface circuit on the test board compensates for environmental differences between the board-type product and the mounting unit. For example, the interface circuit can include a clock distribution circuit, which utilizes a phase locked loop, and a register circuit to compensate for electrical loading caused by the device mounting unit, and to provide the proper timing margins between clock signals and control signals applied to the semiconductor devices.

Abstract: Embodiments of the invention allow semiconductor devices to be tested under actual operating conditions by interfacing the devices to an actual board-type product. The devices are interfaced to the board-type product with a test board that includes a mounting unit such as a socket or pattern of conductive lands that allows the devices to be easily mounted to and removed from the test board with minimal effort and signal degradation. An interface circuit on the test board compensates for environmental differences between the board-type product and the mounting unit. A power control circuit can be used to manipulate the supply voltage applied to the semiconductor devices, thereby providing a voltage margin screening function.

Abstract: A method and apparatus for testing semiconductor devices allows devices to be tested under actual operating conditions by interfacing the devices to an actual board-type product. The semiconductor devices are interfaced to the board-type product with a test board that includes a mounting unit such as a socket or pattern of conductive lands that allows the devices being tested can be easily mounted to and removed from the test board with minimal effort and signal degradation. An interface circuit on the test board compensates for environmental differences between the board-type product and the mounting unit. For example, the interface circuit can include a clock distribution circuit, which utilizes a phase locked loop, and a register circuit to compensate for electrical loading caused by the device mounting unit, and to provide the proper timing margins between clock signals and control signals applied to the semiconductor devices.