Abstract: The present invention provides an apparatus and method of tuning the frequency characteristics of a continuous-time filter. First and second test signals are provided to a filter means and the respective first and second responses of the filter means are measured. The first and second responses are compared and based on the comparison a tuning control signal is provided to the filter means to tune the frequency response characteristics of the filter means. During a tuning phase of operation, a first switch connects a test signal generator and disconnects a data signal generator from the transmission input of a continuous-time filter. A signal processor receives a signal from the transmission output from the continuous-time filter and produces a tuning control signal based on that signal. The test signal generator is comprised of means for providing a first test signal, which may be an alternating signal source ("A.C."), and means for providing a second test signal, which may be a direct signal source ("D.C.

Abstract: A system is disclosed for synthesizing field programmable gate array (FPGA) implementations from high level circuit descriptions. A designer may describe circuits using a textual language or a graphics tool. The system will compile such circuit descriptions into technology mapped descriptions for use with FPGA's.The system will support both random logic circuits and data path circuits. The system uses advanced optimization techniques to produce efficient FPGA implementations. Thus, the system produces high quality results while providing users with a high level of abstraction in design, and thus frees the user from architectural details of the target FPGA.

Abstract: Interconnected cells, such as gates, are partitioned into blocks, such as integrated circuits, wherein the blocks have at least one constraint, such as number of pins available, on the placement of cells therein. The cells are initially assigned to blocks at random or in accordance with a previously-determined initial partition. A quality factor, such as the total number of pins on all blocks, is determined for the initial partition and cells are moved from block to block to form a new partition. The cell moves are selected so as not to violate the constraints and in accordance with the likelihood of improving the overall quality of the partition. Such partitioning is repeated and the overall quality factor is recalculated for each new partition. When the quality factor does not improve substantially from partition to partition, the last partition for which the quality factor improved is selected as the best.

Abstract: A programmable logic cell of a field programmable gate array having a decoder circuit arrangement for increasing the number of inputs to each programmable logic cell. The decoder circuit arrangement couples to the look-up table of each programmable logic cell.