Abstract: A nonvolatile memory device includes an active region extending in a first direction, a first single-layered gate intersecting the active region and extending in a second direction, a second single-layered gate intersecting the active region and extending in the second direction, and a selection gate intersecting the active region. The selection gate includes a first selection gate main line and a second selection gate main line that intersect the active region to be parallel with the first and second single-layered gates, a selection gate interconnection line that connects a first end of the first selection gate main line to a first end of the second selection gate main line, and a selection gate extension that extends from a portion of the selection gate interconnection line to be disposed between first ends of the first and second single-layered gates.

Abstract: A nonvolatile memory device includes a first active region and a second active region separated from each other; a floating gate crossing the first active region, and disposed such that an end thereof overlaps with the second active region; a selection gate crossing the first active region, and disposed side by side with and coupled to the floating gate; a dielectric layer disposed between the floating gate and the selection gate, wherein a stack of the dielectric layer, the floating gate and the selection gate forms a first capacitor in a horizontal structure; a well region disposed in the second active region and coupled to the floating gate, wherein a stack of the well region and the floating gate forms a second capacitor in a vertical structure; and a contact commonly coupled to the well region and the selection gate.

Abstract: A nonvolatile memory device includes a first active region and a second active region separated from each other; a floating gate crossing the first active region, and disposed such that an end thereof overlaps with the second active region; a selection gate crossing the first active region, and disposed side by side with and coupled to the floating gate; a dielectric layer disposed between the floating gate and the selection gate, wherein a stack of the dielectric layer, the floating gate and the selection gate forms a first capacitor in a horizontal structure; a well region disposed in the second active region and coupled to the floating gate, wherein a stack of the well region and the floating gate forms a second capacitor in a vertical structure; and a contact commonly coupled to the well region and the selection gate.

Abstract: Exemplary embodiments of the present invention disclose a light emitting diode including an n-type contact layer doped with silicon, a p-type contact layer, an active region disposed between the n-type contact layer and the p-type contact layer, a superlattice layer disposed between the n-type contact layer and the active region, the superlattice layer including a plurality of layers, an undoped intermediate layer disposed between the superlattice layer and the n-type contact layer, and an electron reinforcing layer disposed between the undoped intermediate layer and the superlattice layer. Only a final layer of the superlattice layer closest to the active region is doped with silicon, and the silicon doping concentration of the final layer is higher than that of the n-type contact layer.

Abstract: Exemplary embodiments of the present invention disclose a light emitting diode including an n-type contact layer doped with silicon, a p-type contact layer, an active region disposed between the n-type contact layer and the p-type contact layer, a superlattice layer disposed between the n-type contact layer and the active region, the superlattice layer including a plurality of layers, an undoped intermediate layer disposed between the superlattice layer and the n-type contact layer, and an electron reinforcing layer disposed between the undoped intermediate layer and the superlattice layer. Only a final layer of the super lattice layer closest to the active region is doped with silicon, and the silicon doping concentration of the final layer is higher than that of the n-type contact layer.

Abstract: A nonvolatile memory device includes a substrate including a device isolation layer defining an active region, a floating gate and a selection gate arranged side by side at intervals of a first gap over the substrate, a coupling plate formed in the device isolation layer and overlapped with the floating gate, and a contact plug suitable for electrically coupling the coupling plate and the selection gate.

Abstract: Exemplary embodiments of the present invention relate to a method of fabricating a light emitting diode (LED). According to an exemplary embodiment of the present invention, the method includes growing a first GaN-based semiconductor layer on a substrate at a first temperature by supplying a chamber with a nitride source gas and a first metal source gas, stopping the supply of the first metal source gas and maintaining the first temperature for a first time period after stopping the supply of the first metal source gas, decreasing the temperature of the substrate to the a second temperature after the first time period elapses, growing an active layer of the first GaN-based semiconductor layer at the second temperature by supplying the chamber with a second metal source gas.

Abstract: Exemplary embodiments of the present invention disclose a light emitting diode including an n-type contact layer doped with silicon, a p-type contact layer, an active region disposed between the n-type contact layer and the p-type contact layer, a superlattice layer disposed between the n-type contact layer and the active region, the superlattice layer including a plurality of layers, an undoped intermediate layer disposed between the superlattice layer and the n-type contact layer, and an electron reinforcing layer disposed between the undoped intermediate layer and the superlattice layer. Only a final layer of the superlattice layer closest to the active region is doped with silicon, and the silicon doping concentration of the final layer is higher than that of the n-type contact layer.

Abstract: A semiconductor device having a common source structure and method of manufacturing the same are provided. In one embodiment, the method includes: forming a plurality of gate lines on a semiconductor substrate, each constituted by a floating gate, a dielectric layer, and a control gate having a line form; forming a first dielectric layer on the semiconductor substrate including the gate line; forming a trench having the line form in the first dielectric layer, wherein the trench exposes the semiconductor substrate between the gate lines; and forming a common source in the trench. According to an embodiment, the common source is implemented as a poly line in the trench. Therefore, etching the substrate to provide a trench for a common source can be excluded. Accordingly, it is possible to inhibit the common source from being opened due to a remaining material in a trench, and reduce damage to the semiconductor substrate.

Abstract: Exemplary embodiments of the present invention relate to a method of fabricating a light emitting diode (LED). According to an exemplary embodiment of the present invention, the method includes growing a first GaN-based semiconductor layer on a substrate at a first temperature by supplying a chamber with a nitride source gas and a first metal source gas, stopping the supply of the first metal source gas and maintaining the first temperature for a first time period after stopping the supply of the first metal source gas, decreasing the temperature of the substrate to the a second temperature after the first time period elapses, growing an active layer of the first GaN-based semiconductor layer at the second temperature by supplying the chamber with a second metal source gas.

Abstract: Exemplary embodiments of the present invention disclose a light emitting diode including an n-type contact layer doped with silicon, a p-type contact layer, an active region disposed between the n-type contact layer and the p-type contact layer, a superlattice layer disposed between the n-type contact layer and the active region, the superlattice layer including a plurality of layers, an undoped intermediate layer disposed between the superlattice layer and the n-type contact layer, and an electron reinforcing layer disposed between the undoped intermediate layer and the superlattice layer. Only a final layer of the superlattice layer closest to the active region is doped with silicon, and the silicon doping concentration of the final layer is higher than that of the n-type contact layer.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a plurality of device isolation layers disposed in a semiconductor substrate, the device isolation layers extending in a word line direction and spaced apart from each other; a plurality of floating gate devices extending in a bit line direction perpendicular to the device isolation layer and spaced apart from each other; a source region and a drain region disposed at sides of the floating gate device; an insulation layer disposed on the floating gate device and the source region, and a polysilicon line extending in the word line direction and connected to the drain region.

Abstract: A semiconductor device having a common source structure and method of manufacturing the same are provided. In one embodiment, the method includes: forming a plurality of gate lines on a semiconductor substrate, each constituted by a floating gate, a dielectric layer, and a control gate having a line form; forming a first dielectric layer on the semiconductor substrate including the gate line; forming a trench having the line form in the first dielectric layer, wherein the trench exposes the semiconductor substrate between the gate lines; and forming a common source in the trench. According to an embodiment, the common source is implemented as a poly line in the trench. Therefore, etching the substrate to provide a trench for a common source can be excluded. Accordingly, it is possible to inhibit the common source from being opened due to a remaining material in a trench, and reduce damage to the semiconductor substrate.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device comprises a plurality of device isolation layers disposed in a semiconductor substrate, the device isolation layers extending in a word line direction and spaced apart from each other; a plurality of floating gate devices extending in a bit line direction perpendicular to the device isolation layer and spaced apart from each other; a source region and a drain region disposed at sides of the floating gate device; an insulation layer disposed on the floating gate device and the source region, and a polysilicon line extending in the word line direction and connected to the drain region.

Abstract: A method of forming a PSG layer on a semiconductor substrate containing semiconductor elements by chemical vapor deposition is characterized in that the concentration of the PSG layer is gradually increased from the substrate surface toward the uppermost surface of the PSG layer.