Abstract: A method for transmitting signals for interference randomization is disclosed. The method for transmitting signals includes spreading the transmission signals using a plurality of orthogonal codes and transmitting the transmission signals spread by the plurality of orthogonal codes by a spatial frequency block coding (SFBC) or spatial time block coding (STBC) scheme. Among the plurality of orthogonal codes, codes of which mutual interferences are equal to or greater than a predetermined threshold are grouped to the same group, and orthogonal codes belonging to different groups are used for the spreading of the signals which are transmitted at the same timing. Accordingly, it is possible to realize interference randomization.

Abstract: The present invention provides for applying a cyclic redundancy check (CRC) to a data signal. The present invention includes attaching a first CRC to a first data signal block having a first length, segmenting the first data signal block attached with the first CRC into a plurality of second data signal blocks having a length shorter than the first length, respectively generating a second CRC for each second data signal block, and attaching the generated second CRC to the respective second data signal block. Moreover, the first CRC and second CRC may be generated from respectively different CRC generating polynomial equations.

Abstract: An apparatus and method for reading written symbols by deinterleaving to decode a written encoder packet in a receiver for a mobile communication system supporting turbo coding and interleaving, such that a turbo-coded/interleaved encoder packet has a bit shift value m, an up-limit value J and a remainder R, and a stream of symbols of the encoder packet is written in order of column to row. The apparatus and method perform the operations of generating an interim address by bit reversal order (BRO) assuming that the remainder R is 0 for the received symbols; calculating an address compensation factor for compensating the interim address in consideration of a column formed with the remainder; and generating a read address by adding the interim address and the address compensation factor for a decoding-required symbol, and reading a symbol written in the generated read address.

Abstract: An apparatus and method for decoding low density parity check (LDPC) codes are provided. A memory module configured by a plurality of unit memories stores a reliability value. Variable node processors perform a computation associated with a variable node, and update data of the memory module in a column direction, respectively. Check node processors perform a computation associated with a check node, and update data of the memory module in a row direction, respectively. A parity checker determines if all errors have been corrected such that an iterative decoding process is performed. A memory access control module selects a unit memory to be updated by a variable node processor or a check node processor.

Abstract: A method for generating block codes from Golay code and a method and apparatus for encoding data are provided. The method can effectively generate codes having various lengths, various dimensions, and superior hamming weight distribution, and encodes data such as control information having various lengths into codes having strong resistance to channel errors, resulting in an increase of error correction performance.

Abstract: A channel coding method of variable length information using block code is disclosed. A method for channel-coding information bits using a code generation matrix including 20 rows and A columns corresponding to length of the information bits includes, channel-coding the information bits having “A” length using basis sequences having 20-bit length corresponding to columns of the code generation matrix. If “A” is 10, individual basis sequences of the code generation matrix correspond to column-directional sequences of a specific matrix composed of 20 rows and 10 columns. The specific matrix is made from 20 rows of the (32,10) code matrix used for TFCI coding were selected.

Abstract: A channel coding method of variable length information using block code is disclosed. A method for channel-coding information bits using a code generation matrix including 32 rows and A columns corresponding to length of the information bits includes, channel-coding the information bits having “A” length using basis sequences having 32-bit length corresponding to columns of the code generation matrix, and outputting the channel-coded result as an output sequence. If “A” is higher than 10, the code generation matrix is generated when (A?10) additional basis sequences were added as column-directional sequences to a first or second matrix. The first matrix is a TFCI code generation matrix composed of 32 rows and 10 columns used for TFCI coding. The second matrix is made when at least one of an inter-row location or an inter-column location of the first matrix was changed. The additional basis sequences satisfy a value 10 of a minimum Hamming distance.

Abstract: The present invention relates to an apparatus and method for detecting a data rate in a turbo decoder for a mobile communication system. When a rate selector selects one data rate among a plurality of data rates, a turbo decoder repeatedly decodes an input data frame within a predetermined repetition limit number using the selected data rate and outputs the decoded data. A CRC detector performs CRC check on the decoded data and outputs the CRC check result, and a decoding state measurer measures decoding quality depending on the decoded data and outputs decoding state information. A controller then sets the repetition limit number to a predetermined minimum value, controls the repetition limit number according to the decoding state information, controls the rate selector and determines a data rate of the input data depending on the CRC check result.

Abstract: The present invention provides for applying a cyclic redundancy check (CRC) to a data signal. The present invention includes attaching a first CRC to a first data signal block having a first length, segmenting the first data signal block attached with the first CRC into a plurality of second data signal blocks having a length shorter than the first length, respectively generating a second CRC for each second data signal block, and attaching the generated second CRC to the respective second data signal block. Moreover, the first CRC and second CRC may be generated from respectively different CRC generating polynomial equations.

Abstract: A method and apparatus for effectively controlling data input to a turbo decoder for decoding forward packet data traffic in a 1xEV-DV mobile station (MS) are disclosed. After received code symbols are stored in one of several memories and read in deinterleaving order, read addresses and chip select signals are generated for the memories based on encoder packet size in synchronization to a decoder clock signal. The decoding starts by inputting a predetermined number of code symbols to the turbo decoder in an appropriate order. The decoder input apparatus reads demodulated forward packet data from decoder input buffers in an appropriate order using the read addresses and chip select signals to generate turbo decoder input data in an appropriate form. Thus, a small-size, low-cost, low-power consumption MS is achieved by processing channel-interleaved data at high speed and with reduced process delay and providing them to a decoder.

Abstract: An apparatus and method for encoding low-density parity check (LDPC) codes. The method for generating a low-density parity check code formed of an information-part matrix and a parity-part matrix comprises the steps of converting the information-part matrix into an array code structure and assigning a degree sequence to each submatrix column; extending a dual-diagonal matrix corresponding to the parity-part matrix such that an offset value between diagonals has a random value; lifting the normalized dual-diagonal matrix; determining an offset value for cyclic column shift for each submatrix of the lifted normalized dual-diagonal matrix; and determining a parity symbol corresponding to a column of the parity-part matrix.

Abstract: A method and apparatus for deshuffling received shuffled data in a communication system supporting multi-level modulation. A transmitter encodes information bits and shuffles code symbols so that systematic symbols having a relatively high priority are disposed at high-transmission reliability positions and parity symbols having a relatively low priority are disposed at low-transmission reliability positions in a modulation symbol. A receiver demodulates received data and outputs a modulation symbol having a plurality of code symbols, stores the code symbols separately as systematic symbols and parity symbols in corresponding memory areas according to a deshuffling order corresponding to the shuffling, reads the stored code symbols, decodes the stored code symbols at a predetermined code rate, and thus outputs an packet.

Abstract: An FEC apparatus and method is provided that uses turbo codes. An input frame is iteratively decoded until an iterative decoding stop command is received under a predetermined control, and the absolute reliability of each symbol in the frame is output. The minimum of the absolute reliabilities is detected as a measurement, and a threshold is detected using the a-priori information and extrinsic information of the each symbol. The measurement is compared with the threshold, and the iterative decoding stop command is output according to the comparison result.

Abstract: An apparatus and method for generating an encoding matrix for a low density parity check (LDPC) code having a dual-diagonal matrix as a parity check matrix are disclosed. The apparatus and method construct an information sub-matrix of the encoding matrix with a predetermined number of square matrixes according to a predetermined code rate such that each of the square matrixes has columns and rows with a weight of 1 and has a different offset value, combine the square matrixes with the dual-diagonal matrix, and perform inter-row permutation on the information sub-matrix.

Abstract: An apparatus and method for encoding low-density parity check (LDPC) codes. The method for generating a low-density parity check code formed of an information-part matrix and a parity-part matrix comprises the steps of converting the information-part matrix into an array code structure and assigning a degree sequence to each submatrix column; extending a dual-diagonal matrix corresponding to the parity-part matrix such that an offset value between diagonals has a random value; lifting the normalized dual-diagonal matrix; determining an offset value for cyclic column shift for each submatrix of the lifted normalized dual-diagonal matrix; and determining a parity symbol corresponding to a column of the parity-part matrix.

Abstract: A forward error correction method for decoding coded bits generated by low density parity check matrixes. The method comprises converting each of the coded bits into a log likelihood ratio (LLR) value, and applying the converted values to variable nodes; delivering messages applied to the variable nodes to check nodes; checking a message having a minimum value among the messages, and determining a sign of the message having the minimum value; receiving messages updated in the check nodes, adding up signs of the received messages and a sign of an initial message, applying a weighting factor of 1 when all signs are identical, and when all signs are not identical, updating a message of a variable node by applying a weighting factor; determining LLR of an initial input value; and hard-deciding values of the variable nodes, performing parity check on the hard decision values, and stopping the decoding when no error occurs.

Abstract: An Forward Error Correction (FEC) apparatus and method for reducing Bit error rates (BER) and Frame Error Rates (FER) using turbo decoding in a digital communication system. In a constituent decoder for decoding a turbo code, a first adder calculates the LLR of a received code symbol by calculating the difference between the probability of the code symbol being 1 and that of the code symbol being 0 at an arbitrary state of a turbo decoding trellis. A second adder adds the transmission information and a priori information of the code symbol. A third adder calculates the difference between the outputs of the first and second adders as extrinsic information. A first multiplier multiplies the output of the third adder by a predetermined weighting factor as a feedback gain. A correction value calculator calculates a correction value using the difference between the best metric and the second best metric of the code symbol. A fourth adder adds the correction value to the output of the first multiplier.

Abstract: Disclosed is an apparatus for stopping iterative decoding in a turbo decoder performing iterative decoding on a received frame comprised of information bits and then outputting the iteratively decoded results. A turbo decoder sequentially outputs absolute LLR (Log Likelihood Ratio) values associated with the respective information bits of the received frame by the iterative decoding, and stops the iterative decoding in response to a stop command for the iterative decoding. A minimum LLR detector selects a minimum value M(i) among the sequentially output absolute LLR values. A controller issues a command to stop the iterative decoding, if the minimum value M(i) is larger than a first threshold determined based on a minimum value Fmin among absolute LLR values output through previous iterative decoding.

Abstract: An apparatus and method for generating an encoding matrix for a low density parity check (LDPC) code having a dual-diagonal matrix as a parity check matrix are disclosed. The apparatus and method construct an information sub-matrix of the encoding matrix with a predetermined number of square matrixes according to a predetermined code rate such that each of the square matrixes has columns and rows with a weight of 1 and has a different offset value, combine the square matrixes with the dual-diagonal matrix, and perform inter-row permutation on the information sub-matrix.

Abstract: An Forward Error Correction (FEC) apparatus and method for reducing Bit error rates (BER) and Frame Error Rates (FER) using turbo decoding in a digital communication system. In a constituent decoder for decoding a turbo code, a first adder calculates the LLR of a received code symbol by calculating the difference between the probability of the code symbol being 1 and that of the code symbol being 0 at an arbitrary state of a turbo decoding trellis. A second adder adds the transmission information and a priori information of the code symbol. A third adder calculates the difference between the outputs of the first and second adders as extrinsic information. A first multiplier multiplies the output of the third adder by a predetermined weighting factor as a feedback gain. A correction value calculator calculates a correction value using the difference between the best metric and the second best metric of the code symbol. A fourth adder adds the correction value to the output of the first multiplier.