Abstract: Described embodiments provide systems and methods for intelligent load balancing of hosted sessions. A processor can determine a plurality of metrics for each of a plurality of machines configured to connect client devices with hosted sessions. The processor can receive, from a client device, a request to establish a connection with one of the plurality of machines to access a hosted session. The processor can determine a score for each of the plurality of machines based at least on the plurality of metrics for each of the plurality of machines. The processor can select a machine from the plurality of machines as a function of the score and a resource cost of the machine. The processor can cause the client device to connect to the selected machine for the hosted session.

Abstract: The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. In accordance with an aspect of the disclosure, a method for providing localized service by a policy control function (PCF) in a wireless communication system, the method comprises receiving, from a localized service provider (LSP), first information including at least one of quality of service (QoS) profiles for different users, and information for time of service, and transmitting, to an access and mobility management function (AMF), second information related to authentication of the at least one user equipment (UE) which is connecting for the localized service.

Abstract: Systems, methods, and computer program products for identifying zones of interest in text transcripts. An application may receive input specifying a text statement type and determine a plurality of heuristics for identifying statements of the statement type in transcripts. The application may determine, based on a first heuristic, a first text statement of the statement type. The application may generate, based on a clustering algorithm, a plurality of additional statements of the statement type. The application may receive a first text transcript. The application may identify, based on a second heuristic, a first text statement in the first text transcript, where the first text transcript statement is of the statement type. The application may generate a graphical indication that the first text transcript statement is of the statement type, and display the first transcript statement and the graphical indication on a display.

Abstract: The present disclosure provides a system (110) for retrofitting words represented using the vectors for Natural Language Processing (NLP) models and a streamlined process which is an ideal pipeline for any NLP tasks. The system (110) may discover the user meta data or k-nuggets in five stages for retrofitting and stacking the retrofitted embeddings. Further, the system (110) may use the retrofitted embeddings for NLP Tasks. The five stages of the k-nugget discovery pipeline are Lexical, Syntactic, Semantic, transactional, and language agnostic stages for retrofitting the word embeddings. The proposed embedding layer is replaced with the retrofitted embedding which may be obtained after the fifth stage and improved performance can be achieved. To validate the approach, the K-nugget discovery pipeline has been tested on the SemEval (Hinglish and English Tweet dataset) and HOT dataset (Hinglish Tweet dataset) and to achieve state of the art results on the test dataset.

Abstract: A coating layer for a substrate includes a coating material. The coating material includes graphene and/or graphene derivatives that reflect and/or absorb an electromagnetic (EM) wave having a frequency of above 20 GHz. The coating layer is deposited on a surface of the substrate.

Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a Zener diode, a first current source, a first n-type field effect transistor (FET), a first inverter circuit, and a second current source. The Zener diode has a cathode coupled to a first node and an anode coupled to a second node. The first current source has a first terminal coupled to the second node and a second terminal coupled to a ground terminal. The first n-type FET has a gate terminal coupled to the second node, a source terminal coupled to the ground terminal, and a drain terminal coupled to a third node. The first inverter circuit has an input coupled to the third node and an output coupled to a fourth node. The second current source has a first terminal coupled to a fifth node and a second terminal coupled to the third node.

Abstract: A method and Network function for controlling an operation of a device based on a service provided to the device is provided. The method includes obtaining at least one of information about the service requested by the device, movement information of the device, or capability information of the device, determining a characteristic of the service provided to the device based on at least one of the information about the service, the movement information of the device, or the capability information of the device, generating service setting information for the service provided to the device based on the determined characteristic of the service, and transmitting, to an Access and Mobility Function (AMF), the service setting information.

Abstract: A method for modeling clock gate timing for an integrated circuit may include creating a dataset having measured values of at least two design features and corresponding measured values of clock gate timing, applying an analytical framework to the dataset to determine how the design features affect the clock gate timing, measuring values of design features for a clock tree for the integrated circuit, and generating predicted values of clock gate timing for the clock tree for the integrated circuit based on how the design features of the dataset affect the clock gate timing of the dataset. The clock tree for the integrated circuit may be a second clock tree, and creating the dataset may include constructing a first clock tree, measuring values of design features of the first clock tree, and measuring corresponding values of clock gate timing of the first clock tree.

Abstract: A method for modeling clock gate timing for an integrated circuit may include creating a dataset having measured values of at least two design features and corresponding measured values of clock gate timing, applying an analytical framework to the dataset to determine how the design features affect the clock gate timing, measuring values of design features for a clock tree for the integrated circuit, and generating predicted values of clock gate timing for the clock tree for the integrated circuit based on how the design features of the dataset affect the clock gate timing of the dataset. The clock tree for the integrated circuit may be a second clock tree, and creating the dataset may include constructing a first clock tree, measuring values of design features of the first clock tree, and measuring corresponding values of clock gate timing of the first clock tree.

Abstract: A method and Network function for controlling an operation of a device based on a service provided to the device is provided. The method includes obtaining at least one of information about the service requested by the device, movement information of the device, or capability information of the device, determining a characteristic of the service provided to the device based on at least one of the information about the service, the movement information of the device, or the capability information of the device, generating service setting information for the service provided to the device based on the determined characteristic of the service, and transmitting, to an Access and Mobility Function (AMF), the service setting information.

Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a Zener diode, a first current source, a first n-type field effect transistor (FET), a first inverter circuit, and a second current source. The Zener diode has a cathode coupled to a first node and an anode coupled to a second node. The first current source has a first terminal coupled to the second node and a second terminal coupled to a ground terminal. The first n-type FET has a gate terminal coupled to the second node, a source terminal coupled to the ground terminal, and a drain terminal coupled to a third node. The first inverter circuit has an input coupled to the third node and an output coupled to a fourth node. The second current source has a first terminal coupled to a fifth node and a second terminal coupled to the third node.

Abstract: An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower-order counter sub-module. The control logic includes a clock-gating integrated cell arranged to clock gate at least one higher-order counter sub-module dependent on a logical combination of outputs of the lower-order counter sub-module and to provide a multi-cycle path for resolution of a logical combination of outputs of any subsequent cascaded counter sub-modules. The control logic does not include any intervening memory device between the lower-order counter sub-module and the clock-gating integrated cell for use in determining a later control logic output.

Abstract: An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower-order counter sub-module. The control logic includes a clock-gating integrated cell arranged to clock gate at least one higher-order counter sub-module dependent on a logical combination of outputs of the lower-order counter sub-module and to provide a multi-cycle path for resolution of a logical combination of outputs of any subsequent cascaded counter sub-modules. The control logic does not include any intervening memory device between the lower-order counter sub-module and the clock-gating integrated cell for use in determining a later control logic output.

Abstract: A Gray code counter has multiple two-bit Gray code counter modules, clock gated integrated cells (CGICs), and a parity bit generator. The CGICs gate clock signals provided to the two-bit counter modules, which reduces dynamic power consumption. The parity bit generator generates a parity bit that indicates a count of binary ones in a counting state.

Abstract: A hybrid counter generates a multi-bit hybrid counter value. The hybrid counter includes two or more asynchronous counters, each configured to generate a subset of the bits of the multi-bit hybrid counter value. The asynchronous counters are interconnected by a logic gate and a clock gating circuit. The logic gate generates an asynchronous logic value based on the bits generated by the previous asynchronous counters. The clock gating circuit re-times the asynchronous logic value to generate a synchronous logic value that is used to toggle the next asynchronous counter. The hybrid counter functions more accurately than conventional asynchronous counters and with less power than conventional synchronous counters.

Abstract: A method of generating test patterns for testing a semiconductor processor for small delay defects (SDD) includes modifying interconnect delay values of interconnect paths by introducing values corresponding to (i) set-up and clock to Q delays of elements in the paths and (ii) latencies of associated clock networks. Critical nodes are selected and test patterns targeting the selected critical nodes are generated using timing slack resulting from the modified interconnect delays. A first selection of nodes that are critical in at-speed scan mode testing and a second selection of nodes that are critical in functional mode testing are made by static timing analysis (STA). Only the nodes featuring in both the first and second selections are selected for targeting small delay defects using at-speed scan test patterns.

Abstract: A hybrid counter generates a multi-bit hybrid counter value. The hybrid counter includes two or more asynchronous counters, each configured to generate a subset of the bits of the multi-bit hybrid counter value. The asynchronous counters are interconnected by a logic gate and a clock gating circuit. The logic gate generates an asynchronous logic value based on the bits generated by the previous asynchronous counters. The clock gating circuit re-times the asynchronous logic value to generate a synchronous logic value that is used to toggle the next asynchronous counter. The hybrid counter functions more accurately than conventional asynchronous counters and with less power than conventional synchronous counters.

Abstract: An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower order counter sub-module. The control logic is arranged to clock gate at least one higher order counter sub-module dependent on a logical combination of outputs of the lower order counter sub-module and where the control logic uses pipelining to store at least one previous control logic output for use in determining a later control logic output.

Abstract: A Gray code counter has multiple two-bit Gray code counter modules, clock gated integrated cells (CGICs), and a parity bit generator. The CGICs gate clock signals provided to the two-bit counter modules, which reduces dynamic power consumption. The parity bit generator generates a parity bit that indicates a count of binary ones in a counting state.

Abstract: An adder circuit includes first through fourth two-bit adder modules, and first through third result mux blocks for receiving and adding first and second binary values to generate a final sum. A multiplier circuit that multiplies a multiplier and a multiplicand includes a multiplexer, an encoder connected to the multiplexer, a shifter connected to the encoder, and an accumulator connected to the encoder for receiving the multiplier and multiplicand and generating a multiplication product.