Patents by Inventor Naman Gupta

Naman Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250142327
    Abstract: The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. According to an embodiment of the disclosure, a method performed by a user equipment (UE) comprises transmitting, to a UDM (unified data management), a first message for credentials for the UE, the credentials for the UE including at least one of name information, a mobile phone number, and a date of birth. The method comprises receiving, from the UDM, a second message indicating authentication success, wherein the second message includes a user ID corresponding to the credentials for the UE. The method comprises receiving, from an AMF (access and mobility management function), a third message to trigger local authentication of the UE. The method comprises performing the local authentication for the UE based on the second message and the third message.
    Type: Application
    Filed: October 25, 2024
    Publication date: May 1, 2025
    Inventors: Naman GUPTA, Jicheol LEE
  • Publication number: 20250053866
    Abstract: A method for sharing data between machine learning (ML) applications with a network training platform. The method includes: receiving a request to register a first ML application with the network training platform, wherein the request comprises first one or more parameters related to the first ML application; identifying at least one second ML application registered with the network training platform based on the first one or more parameters; identifying second one or more parameters related to the at least one second ML application; comparing the first one or more parameters with the second one or more parameters related to the at least one second ML application; and sharing, with the first ML application, predicted data corresponding to the at least one second ML application based on the comparing.
    Type: Application
    Filed: March 27, 2024
    Publication date: February 13, 2025
    Inventors: Subhash Kumar SINGH, Sukhdeep SINGH, Naman GUPTA, Peter Moonki HONG, Seungil YOON
  • Patent number: 12182513
    Abstract: The present disclosure provides a system (110) for retrofitting words represented using the vectors for Natural Language Processing (NLP) models and a streamlined process which is an ideal pipeline for any NLP tasks. The system (110) may discover the user meta data or k-nuggets in five stages for retrofitting and stacking the retrofitted embeddings. Further, the system (110) may use the retrofitted embeddings for NLP Tasks. The five stages of the k-nugget discovery pipeline are Lexical, Syntactic, Semantic, transactional, and language agnostic stages for retrofitting the word embeddings. The proposed embedding layer is replaced with the retrofitted embedding which may be obtained after the fifth stage and improved performance can be achieved. To validate the approach, the K-nugget discovery pipeline has been tested on the SemEval (Hinglish and English Tweet dataset) and HOT dataset (Hinglish Tweet dataset) and to achieve state of the art results on the test dataset.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: December 31, 2024
    Assignee: JIO PLATFORMS LIMITED
    Inventors: Prasad Pradip Joshi, Chinesh Doshi, Naman Gupta
  • Publication number: 20240388641
    Abstract: The disclosure relates to a 5th generation (5G) or 6th generation (6G) communication system for supporting a higher data transmission rate.
    Type: Application
    Filed: May 17, 2024
    Publication date: November 21, 2024
    Inventors: Kisuk KWEON, Naman GUPTA
  • Publication number: 20240155343
    Abstract: The disclosure relates to a fifth-generation (5G) or sixth-generation (6G) communication system for supporting a higher data transmission rate. A method performed by a user plane function (UPF) entity in a wireless communication system is provided. The method includes receiving, from a network entity requesting a subscription of a UPF service, a UPF service subscription request message, identifying whether an authorization of the UPF service is required and an entity associated with the authorization of the UPF service, transmitting, to the entity associated with the authorization of the UPF service, an authorization request message for the UPF service, receiving, from the entity associated with the authorization of the UPF service, an authorization response message for the UPF service.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 9, 2024
    Inventors: Kisuk KWEON, Naman GUPTA
  • Publication number: 20240147553
    Abstract: The disclosure relates to a 5th generation (5G) communication system or a 6th generation (6G) communication system for supporting higher data transmission rates. A method is provided for a user plane function (UPF) in a wireless communication system.
    Type: Application
    Filed: November 2, 2023
    Publication date: May 2, 2024
    Inventors: Kisuk KWEON, Naman GUPTA, Sangsoo JEONG
  • Publication number: 20240048982
    Abstract: The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. In accordance with an aspect of the disclosure, a method for providing localized service by a policy control function (PCF) in a wireless communication system, the method comprises receiving, from a localized service provider (LSP), first information including at least one of quality of service (QoS) profiles for different users, and information for time of service, and transmitting, to an access and mobility management function (AMF), second information related to authentication of the at least one user equipment (UE) which is connecting for the localized service.
    Type: Application
    Filed: August 3, 2023
    Publication date: February 8, 2024
    Inventors: Naman GUPTA, Kisuk KWEON
  • Publication number: 20230196035
    Abstract: Systems, methods, and computer program products for identifying zones of interest in text transcripts. An application may receive input specifying a text statement type and determine a plurality of heuristics for identifying statements of the statement type in transcripts. The application may determine, based on a first heuristic, a first text statement of the statement type. The application may generate, based on a clustering algorithm, a plurality of additional statements of the statement type. The application may receive a first text transcript. The application may identify, based on a second heuristic, a first text statement in the first text transcript, where the first text transcript statement is of the statement type. The application may generate a graphical indication that the first text transcript statement is of the statement type, and display the first transcript statement and the graphical indication on a display.
    Type: Application
    Filed: December 17, 2021
    Publication date: June 22, 2023
    Applicant: Capital One Services, LLC
    Inventors: Akshay Aravindakshan THONIPARAMBIL, Naman GUPTA, Manish AGARWAL, Sourav CHOUDHARY
  • Publication number: 20230092651
    Abstract: The present disclosure provides a system (110) for retrofitting words represented using the vectors for Natural Language Processing (NLP) models and a streamlined process which is an ideal pipeline for any NLP tasks. The system (110) may discover the user meta data or k-nuggets in five stages for retrofitting and stacking the retrofitted embeddings. Further, the system (110) may use the retrofitted embeddings for NLP Tasks. The five stages of the k-nugget discovery pipeline are Lexical, Syntactic, Semantic, transactional, and language agnostic stages for retrofitting the word embeddings. The proposed embedding layer is replaced with the retrofitted embedding which may be obtained after the fifth stage and improved performance can be achieved. To validate the approach, the K-nugget discovery pipeline has been tested on the SemEval (Hinglish and English Tweet dataset) and HOT dataset (Hinglish Tweet dataset) and to achieve state of the art results on the test dataset.
    Type: Application
    Filed: August 31, 2022
    Publication date: March 23, 2023
    Applicant: Jio Platforms Limited
    Inventors: Prasad Pradip JOSHI, Chinesh DOSHI, Naman GUPTA
  • Publication number: 20230082231
    Abstract: A coating layer for a substrate includes a coating material. The coating material includes graphene and/or graphene derivatives that reflect and/or absorb an electromagnetic (EM) wave having a frequency of above 20 GHz. The coating layer is deposited on a surface of the substrate.
    Type: Application
    Filed: September 10, 2021
    Publication date: March 16, 2023
    Inventors: Yong Lak Joo, Naman Gupta, Somayeh Zamani, Yash Joshi, Ryota Okumura, Shinichi Ito, Elizabeth Izor
  • Patent number: 11293954
    Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a Zener diode, a first current source, a first n-type field effect transistor (FET), a first inverter circuit, and a second current source. The Zener diode has a cathode coupled to a first node and an anode coupled to a second node. The first current source has a first terminal coupled to the second node and a second terminal coupled to a ground terminal. The first n-type FET has a gate terminal coupled to the second node, a source terminal coupled to the ground terminal, and a drain terminal coupled to a third node. The first inverter circuit has an input coupled to the third node and an output coupled to a fourth node. The second current source has a first terminal coupled to a fifth node and a second terminal coupled to the third node.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: April 5, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Naman Gupta, Rajat Chauhan, Santhosh Kumar Srinivasan
  • Patent number: 11284240
    Abstract: A method and Network function for controlling an operation of a device based on a service provided to the device is provided. The method includes obtaining at least one of information about the service requested by the device, movement information of the device, or capability information of the device, determining a characteristic of the service provided to the device based on at least one of the information about the service, the movement information of the device, or the capability information of the device, generating service setting information for the service provided to the device based on the determined characteristic of the service, and transmitting, to an Access and Mobility Function (AMF), the service setting information.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: March 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Satish Kumar, Sukhdeep Singh, Suman Kumar, Avinash Bhat, Rahul Banerji, Naman Gupta, Seungil Yoon
  • Patent number: 11042678
    Abstract: A method for modeling clock gate timing for an integrated circuit may include creating a dataset having measured values of at least two design features and corresponding measured values of clock gate timing, applying an analytical framework to the dataset to determine how the design features affect the clock gate timing, measuring values of design features for a clock tree for the integrated circuit, and generating predicted values of clock gate timing for the clock tree for the integrated circuit based on how the design features of the dataset affect the clock gate timing of the dataset. The clock tree for the integrated circuit may be a second clock tree, and creating the dataset may include constructing a first clock tree, measuring values of design features of the first clock tree, and measuring corresponding values of clock gate timing of the first clock tree.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: June 22, 2021
    Inventors: Naman Gupta, Vinayak Kini, Hongda Lu
  • Publication number: 20200401669
    Abstract: A method for modeling clock gate timing for an integrated circuit may include creating a dataset having measured values of at least two design features and corresponding measured values of clock gate timing, applying an analytical framework to the dataset to determine how the design features affect the clock gate timing, measuring values of design features for a clock tree for the integrated circuit, and generating predicted values of clock gate timing for the clock tree for the integrated circuit based on how the design features of the dataset affect the clock gate timing of the dataset. The clock tree for the integrated circuit may be a second clock tree, and creating the dataset may include constructing a first clock tree, measuring values of design features of the first clock tree, and measuring corresponding values of clock gate timing of the first clock tree.
    Type: Application
    Filed: October 25, 2019
    Publication date: December 24, 2020
    Inventors: Naman GUPTA, Vinayak KINI, Hongda LU
  • Publication number: 20200296569
    Abstract: A method and Network function for controlling an operation of a device based on a service provided to the device is provided. The method includes obtaining at least one of information about the service requested by the device, movement information of the device, or capability information of the device, determining a characteristic of the service provided to the device based on at least one of the information about the service, the movement information of the device, or the capability information of the device, generating service setting information for the service provided to the device based on the determined characteristic of the service, and transmitting, to an Access and Mobility Function (AMF), the service setting information.
    Type: Application
    Filed: March 9, 2020
    Publication date: September 17, 2020
    Inventors: Satish KUMAR, Sukhdeep SINGH, Suman KUMAR, Avinash BHAT, Rahul BANERJI, Naman GUPTA, Seungil YOON
  • Publication number: 20200018782
    Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a Zener diode, a first current source, a first n-type field effect transistor (FET), a first inverter circuit, and a second current source. The Zener diode has a cathode coupled to a first node and an anode coupled to a second node. The first current source has a first terminal coupled to the second node and a second terminal coupled to a ground terminal. The first n-type FET has a gate terminal coupled to the second node, a source terminal coupled to the ground terminal, and a drain terminal coupled to a third node. The first inverter circuit has an input coupled to the third node and an output coupled to a fourth node. The second current source has a first terminal coupled to a fifth node and a second terminal coupled to the third node.
    Type: Application
    Filed: March 25, 2019
    Publication date: January 16, 2020
    Inventors: Naman GUPTA, Rajat CHAUHAN, Santhosh Kumar SRINIVASAN
  • Patent number: 9438248
    Abstract: An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower-order counter sub-module. The control logic includes a clock-gating integrated cell arranged to clock gate at least one higher-order counter sub-module dependent on a logical combination of outputs of the lower-order counter sub-module and to provide a multi-cycle path for resolution of a logical combination of outputs of any subsequent cascaded counter sub-modules. The control logic does not include any intervening memory device between the lower-order counter sub-module and the clock-gating integrated cell for use in determining a later control logic output.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: September 6, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Naman Gupta, Amol Agarwal, Gaurav Goyal
  • Publication number: 20160173106
    Abstract: An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower-order counter sub-module. The control logic includes a clock-gating integrated cell arranged to clock gate at least one higher-order counter sub-module dependent on a logical combination of outputs of the lower-order counter sub-module and to provide a multi-cycle path for resolution of a logical combination of outputs of any subsequent cascaded counter sub-modules. The control logic does not include any intervening memory device between the lower-order counter sub-module and the clock-gating integrated cell for use in determining a later control logic output.
    Type: Application
    Filed: December 12, 2014
    Publication date: June 16, 2016
    Inventors: Naman Gupta, Amol Agarwal, Gaurav Goyal
  • Patent number: 9306576
    Abstract: A Gray code counter has multiple two-bit Gray code counter modules, clock gated integrated cells (CGICs), and a parity bit generator. The CGICs gate clock signals provided to the two-bit counter modules, which reduces dynamic power consumption. The parity bit generator generates a parity bit that indicates a count of binary ones in a counting state.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: April 5, 2016
    Assignee: FREESCALE SEMICONDUCTOR,INC.
    Inventors: Naman Gupta, Gaurav Goyal, Rohit Goyal
  • Patent number: 9294099
    Abstract: A hybrid counter generates a multi-bit hybrid counter value. The hybrid counter includes two or more asynchronous counters, each configured to generate a subset of the bits of the multi-bit hybrid counter value. The asynchronous counters are interconnected by a logic gate and a clock gating circuit. The logic gate generates an asynchronous logic value based on the bits generated by the previous asynchronous counters. The clock gating circuit re-times the asynchronous logic value to generate a synchronous logic value that is used to toggle the next asynchronous counter. The hybrid counter functions more accurately than conventional asynchronous counters and with less power than conventional synchronous counters.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: March 22, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Rohit Goyal, Deepak Kumar Behera, Naman Gupta