Patents by Inventor Namasivayam Thangavelu

Namasivayam Thangavelu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SYSTEMS AND METHODS FOR ENCOURAGING PATIENT BEHAVIOR
    Publication number: 20210158722
    Abstract: Various systems and methods for encouraging patient behavior utilize one or more sensors for gathering medical-related information about a patient and processing the medical-related information to provide feedback to the patient, such as notification reminders for dosing, testing, and/or other patient behaviors.
    Type: Application
    Filed: December 4, 2020
    Publication date: May 27, 2021
    Inventors: Bhavik VYAS, Namasivayam THANGAVELU
  • Cache flushing
    Patent number: 7380063
    Abstract: Portions of a cache are flushed in stages. An exemplary flushing of the present invention comprises flushing a first portion, performing operations other than a flush, and then flushing a second portion of the cache. The first portion may be disabled after it is flushed. The cache may be functionally divided into portions prior to a flush, or the portions may be determined in part by an abort signal. The operations may access either the cache or the memory. The operations may involve direct memory access or interrupt servicing.
    Type: Grant
    Filed: June 20, 2006
    Date of Patent: May 27, 2008
    Assignee: Intel Corporation
    Inventors: John W. Horrigan, Namasivayam Thangavelu, George Vargese, Brian Holscher
  • Cache flushing
    Publication number: 20070005900
    Abstract: Portions of a cache are flushed in stages. An exemplary flushing of the present invention comprises flushing a first portion, performing operations other than a flush, and then flushing a second portion of the cache. The first portion may be disabled after it is flushed. The cache may be functionally divided into portions prior to a flush, or the portions may be determined in part by an abort signal. The operations may access either the cache or the memory. The operations may involve direct memory access or interrupt servicing.
    Type: Application
    Filed: June 20, 2006
    Publication date: January 4, 2007
    Inventors: John Horrigan, Namasivayam Thangavelu, Varghese George, Brian Holscher
  • Cache flushing
    Patent number: 7089366
    Abstract: Portions of a cache are flushed in stages. An exemplary flushing of the present invention comprises flushing a first portion, performing operations other than a flush, and then flushing a second portion of the cache. The first portion may be disabled after it is flushed. The cache may be functionally divided into portions prior to a flush, or the portions may be determined in part by an abort signal. The operations may access either the cache or the memory. The operations may involve direct memory access or interrupt servicing.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: August 8, 2006
    Assignee: Intel Corporation
    Inventors: John W. Horrigan, Namasivayam Thangavelu, George Vargese, Brian Holscher
  • Cache flushing
    Publication number: 20040073751
    Abstract: Portions of a cache are flushed in stages. An exemplary flushing of the present invention comprises flushing a first portion, performing operations other than a flush, and then flushing a second portion of the cache. The first portion may be disabled after it is flushed. The cache may be functionally divided into portions prior to a flush, or the portions may be determined in part by an abort signal. The operations may access either the cache or the memory. The operations may involve direct memory access or interrupt servicing.
    Type: Application
    Filed: October 8, 2003
    Publication date: April 15, 2004
    Applicant: Intel Corporation
    Inventors: John W. Horrigan, Namasivayam Thangavelu, Varghese George, Brian Holscher
  • Cache flushing
    Patent number: 6658532
    Abstract: Portions of a cache are flushed in stages. An exemplary flushing of the present invention comprises flushing a first portion, performing operations other than a flush, and then flushing a second portion of the cache. The first portion may be disabled after it is flushed. The cache may be functionally divided into portions prior to a flush, or the portions may be determined in part by an abort signal. The operations may access either the cache or the memory. The operations may involve direct memory access or interrupt servicing.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: December 2, 2003
    Assignee: Intel Corporation
    Inventors: John W. Horrigan, Namasivayam Thangavelu, George Vargese, Brian Holscher