Patents by Inventor Nam-Gyu BAEK
Nam-Gyu BAEK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11158589Abstract: A semiconductor device has a semiconductor chip region which contains a semiconductor chip and a first portion of a passivation film covering the semiconductor chip and a scribe line region which contains a second portion of the passivation film connected to the first portion of the passivation film, a first insulating film protruding from a distal end of the second portion of the passivation film, and at least a part of a first wiring. A first portion of the first insulating film is disposed along the distal end of the second portion of the passivation film, a second portion of the first insulating film protrudes laterally beyond the first portion of the first insulating film, and the first wiring protrudes laterally beyond the second portion of the first insulating film.Type: GrantFiled: August 6, 2019Date of Patent: October 26, 2021Assignee: Samsung Electronics Co., LtdInventors: Seung Hun Han, Yun Rae Cho, Nam Gyu Baek, Ae Nee Jang
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Patent number: 10643958Abstract: Provided is a semiconductor device including a semiconductor substrate including a main chip area and a scribe lane area adjacent to the main chip area, the scribe lane area including a first region adjacent to the main chip area and a second region adjacent to the first region; an insulating layer disposed on the semiconductor substrate; first embossing structures disposed on a first surface of the insulating layer in a first area of the insulating layer corresponding to the first region; second embossing structures disposed on the first surface of the insulating layer in a second area of the insulating layer corresponding to the second region; and dam structures provided in the first area of the insulating layer at positions corresponding to the first embossing structures, the dam structures extending in a direction perpendicular to a second surface of the insulating layer that is adjacent to the semiconductor substrate.Type: GrantFiled: October 12, 2018Date of Patent: May 5, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun-dae Kim, Hyung-gil Baek, Yun-rae Cho, Nam-gyu Baek
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Publication number: 20200051932Abstract: A semiconductor device has a semiconductor chip region which contains a semiconductor chip and a first portion of a passivation film covering the semiconductor chip and a scribe line region which contains a second portion of the passivation film connected to the first portion of the passivation film, a first insulating film protruding from a distal end of the second portion of the passivation film, and at least a part of a first wiring. A first portion of the first insulating film is disposed along the distal end of the second portion of the passivation film, a second portion of the first insulating film protrudes laterally beyond the first portion of the first insulating film, and the first wiring protrudes laterally beyond the second portion of the first insulating film.Type: ApplicationFiled: August 6, 2019Publication date: February 13, 2020Inventors: SEUNG HUN HAN, YUN RAE CHO, NAM GYU BAEK, AE NEE JANG
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Publication number: 20200035649Abstract: A semiconductor package includes a package substrate, a plurality of external connections under the package substrate, a master chip on the package substrate, at least one slave chip on the master chip, a plurality of first bumps and a plurality of second bumps between the package substrate and the master chip, and a plurality of wires connecting the package substrate to the at least one slave chip. The package substrate includes a plurality of first paths connecting the plurality of first bumps to the plurality of external connections and a plurality of second paths connecting the plurality of second bumps to the plurality of wires. An upper surface of the package substrate includes a first edge and a second edge that extend in a first direction and a third edge and a fourth edge that extend in a second direction.Type: ApplicationFiled: April 5, 2019Publication date: January 30, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Ae-nee JANG, Nam-gyu BAEK, Yun-rae CHO, Seung-hun HAN
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Patent number: 10490514Abstract: The semiconductor devices may include a semiconductor substrate, and a guard ring and a crack sensing circuit on the semiconductor substrate. The semiconductor substrate may include a main chip region that is defined by the guard ring and includes the crack sensing circuit, a central portion of the main chip region surrounded by the crack sensing circuit, and a chamfer region that is in a corner portion of the main chip region and is defined by the guard ring and the crack sensing circuit. The semiconductor devices may also include at least one gate structure on the semiconductor substrate in the main chip region, a plurality of metal pattern structures on the at least one gate structure in the chamfer region, and an insulating layer on the plurality of metal pattern structures. The plurality of metal pattern structures may extend in parallel to one another and may have different lengths.Type: GrantFiled: April 12, 2019Date of Patent: November 26, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-Gyu Baek, Yun-Rae Cho, Hyung-Gil Baek, Sun-Dae Kim
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Publication number: 20190237414Abstract: The semiconductor devices may include a semiconductor substrate, and a guard ring and a crack sensing circuit on the semiconductor substrate. The semiconductor substrate may include a main chip region that is defined by the guard ring and includes the crack sensing circuit, a central portion of the main chip region surrounded by the crack sensing circuit, and a chamfer region that is in a corner portion of the main chip region and is defined by the guard ring and the crack sensing circuit. The semiconductor devices may also include at least one gate structure on the semiconductor substrate in the main chip region, a plurality of metal pattern structures on the at least one gate structure in the chamfer region, and an insulating layer on the plurality of metal pattern structures. The plurality of metal pattern structures may extend in parallel to one another and may have different lengths.Type: ApplicationFiled: April 12, 2019Publication date: August 1, 2019Inventors: NAM-GYU BAEK, YUN-RAE CHO, HYUNG-GIL BAEK, SUN-DAE KIM
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Patent number: 10304781Abstract: The semiconductor devices may include a semiconductor substrate, and a guard ring and a crack sensing circuit on the semiconductor substrate. The semiconductor substrate may include a main chip region that is defined by the guard ring and includes the crack sensing circuit, a central portion of the main chip region surrounded by the crack sensing circuit, and a chamfer region that is in a corner portion of the main chip region and is defined by the guard ring and the crack sensing circuit. The semiconductor devices may also include at least one gate structure on the semiconductor substrate in the main chip region, a plurality of metal pattern structures on the at least one gate structure in the chamfer region, and an insulating layer on the plurality of metal pattern structures. The plurality of metal pattern structures may extend in parallel to one another and may have different lengths.Type: GrantFiled: March 15, 2017Date of Patent: May 28, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-gyu Baek, Yun-rae Cho, Hyung-gil Baek, Sun-dae Kim
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Publication number: 20190139921Abstract: A semiconductor device includes a substrate, a contact pad arranged in the substrate, a bump arranged on the contact pad to be electrically connected with the contact pad, an insulating film arranged on the substrate to surround a side surface of the bump and to expose at least a portion of the contact pad to the bump, and a photosensitive film which is formed on the insulating film and comprises a polyimide, wherein the photosensitive film comprises a first region surrounding the side surface of the bump and having a first thickness measured in a vertical direction, and a second region arranged on the first region and having a second thickness thickermeasured in the vertical direction, wherein the second region is spaced apart from the bump in a horizontal direction, and wherein the second thickness is greater than a thickness two times thicker than a difference value between the second thickness and the first thickness.Type: ApplicationFiled: July 9, 2018Publication date: May 9, 2019Inventors: Nam Gyu BAEK, In Young LEE, Hyun Soo CHUNG, Ho Geon SONG
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Publication number: 20190043813Abstract: Provided is a semiconductor device including a semiconductor substrate including a main chip area and a scribe lane area adjacent to the main chip area, the scribe lane area including a first region adjacent to the main chip area and a second region adjacent to the first region; an insulating layer disposed on the semiconductor substrate; first embossing structures disposed on a first surface of the insulating layer in a first area of the insulating layer corresponding to the first region; second embossing structures disposed on the first surface of the insulating layer in a second area of the insulating layer corresponding to the second region; and dam structures provided in the first area of the insulating layer at positions corresponding to the first embossing structures, the dam structures extending in a direction perpendicular to a second surface of the insulating layer that is adjacent to the semiconductor substrate.Type: ApplicationFiled: October 12, 2018Publication date: February 7, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun-dae KIM, Hyung-gil BAEK, Yun-rae CHO, Nam-gyu BAEK
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Patent number: 10103109Abstract: Provided is a semiconductor device including a semiconductor substrate including a main chip area and a scribe lane area adjacent to the main chip area, the scribe lane area including a first region adjacent to the main chip area and a second region adjacent to the first region; an insulating layer disposed on the semiconductor substrate; first embossing structures disposed on a first surface of the insulating layer in a first area of the insulating layer corresponding to the first region; second embossing structures disposed on the first surface of the insulating layer in a second area of the insulating layer corresponding to the second region; and dam structures provided in the first area of the insulating layer at positions corresponding to the first embossing structures, the dam structures extending in a direction perpendicular to a second surface of the insulating layer that is adjacent to the semiconductor substrate.Type: GrantFiled: March 2, 2017Date of Patent: October 16, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun-dae Kim, Hyung-gil Baek, Yun-rae Cho, Nam-gyu Baek
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Patent number: 9984945Abstract: A semiconductor chip may include a semiconductor substrate and a crack detection circuit. The semiconductor substrate may include a circuit structure. The crack detection circuit may include main lines and a chamfer lines. The main lines may be formed in the semiconductor substrate to surround the circuit structure. The chamfer lines may be formed in corners of the semiconductor substrate. The chamfer lines may be connected between the main lines. A first angle may be formed between each of the chamfer lines and any one of the two main lines perpendicular to each other. A second angle wider than the first angle may be formed between each of the chamfer lines and the other main line.Type: GrantFiled: July 26, 2016Date of Patent: May 29, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Yun-Rae Cho, Sun-Dae Kim, Nam-Gyu Baek, Hyung-Gil Baek
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Publication number: 20170345773Abstract: The semiconductor devices may include a semiconductor substrate, and a guard ring and a crack sensing circuit on the semiconductor substrate. The semiconductor substrate may include a main chip region that is defined by the guard ring and includes the crack sensing circuit, a central portion of the main chip region surrounded by the crack sensing circuit, and a chamfer region that is in a corner portion of the main chip region and is defined by the guard ring and the crack sensing circuit. The semiconductor devices may also include at least one gate structure on the semiconductor substrate in the main chip region, a plurality of metal pattern structures on the at least one gate structure in the chamfer region, and an insulating layer on the plurality of metal pattern structures. The plurality of metal pattern structures may extend in parallel to one another and may have different lengths.Type: ApplicationFiled: March 15, 2017Publication date: November 30, 2017Inventors: Nam-gyu BAEK, Yun-rae Cho, Hyung-gil Baek, Sun-dae Kim
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Publication number: 20170317035Abstract: Provided is a semiconductor device including a semiconductor substrate including a main chip area and a scribe lane area adjacent to the main chip area, the scribe lane area including a first region adjacent to the main chip area and a second region adjacent to the first region; an insulating layer disposed on the semiconductor substrate; first embossing structures disposed on a first surface of the insulating layer in a first area of the insulating layer corresponding to the first region; second embossing structures disposed on the first surface of the insulating layer in a second area of the insulating layer corresponding to the second region; and dam structures provided in the first area of the insulating layer at positions corresponding to the first embossing structures, the dam structures extending in a direction perpendicular to a second surface of the insulating layer that is adjacent to the semiconductor substrate.Type: ApplicationFiled: March 2, 2017Publication date: November 2, 2017Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun-dae Kim, Hyung-gil Baek, Yun-rae Cho, Nam-gyu Baek
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Patent number: 9698066Abstract: A semiconductor chip includes: a gate pattern on a substrate; an interlayer insulation layer on the gate pattern; a first wiring structure on the interlayer insulation layer; and a defect detection circuit electrically connected to the gate pattern and the first wiring structure. The first wiring structure is electrically connected to the gate pattern via a contact plug through the interlayer insulation layer. The defect detection circuit is electrically connected to the gate pattern and the first wiring structure, and the defect detection circuit is configured to detect defects in the first wiring structure and at least one of the gate pattern and the substrate.Type: GrantFiled: July 5, 2016Date of Patent: July 4, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Bo-Ra Lee, Jae-Ho Jeong, Nam-Gyu Baek, Hyo-Seok Woo, Hyun-Sook Yoon, Kwang-Yong Lee
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Publication number: 20170103929Abstract: A semiconductor chip includes: a gate pattern on a substrate; an interlayer insulation layer on the gate pattern; a first wiring structure on the interlayer insulation layer; and a defect detection circuit electrically connected to the gate pattern and the first wiring structure. The first wiring structure is electrically connected to the gate pattern via a contact plug through the interlayer insulation layer. The defect detection circuit is electrically connected to the gate pattern and the first wiring structure, and the defect detection circuit is configured to detect defects in the first wiring structure and at least one of the gate pattern and the substrate.Type: ApplicationFiled: July 5, 2016Publication date: April 13, 2017Inventors: Bo-Ra LEE, Jae-Ho JEONG, Nam-Gyu BAEK, Hyo-Seok WOO, Hyun-Sook YOON, Kwang-Yong LEE
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Publication number: 20170062293Abstract: A semiconductor chip may include a semiconductor substrate and a crack detection circuit. The semiconductor substrate may include a circuit structure. The crack detection circuit may include main lines and a chamfer lines. The main lines may be formed in the semiconductor substrate to surround the circuit structure. The chamfer lines may be formed in corners of the semiconductor substrate. The chamfer lines may be connected between the main lines. A first angle may be formed between each of the chamfer lines and any one of the two main lines perpendicular to each other. A second angle wider than the first angle may be formed between each of the chamfer lines and the other main line. Thus, although a crack may be generated in the corner of the semiconductor substrate by twice cutting processes of a wafer, the crack detection circuit may not detect the crack.Type: ApplicationFiled: July 26, 2016Publication date: March 2, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Yun-Rae Cho, Sun-Dae Kim, Nam-Gyu Baek, Hyung-Gil Baek
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Patent number: 9570411Abstract: A pad structure usable with a semiconductor device may include an insulating layer pattern structure, a plug, and a pad. The insulating layer pattern structure has a plug hole and at least one via hole. The plug is formed in the plug hole. The pad is formed on the insulating layer pattern structure. The pad is electrically connected with the plug and has a lower surface and an uneven upper surface. The lower surface includes a protruded portion inserted into the via hole. The uneven upper surface includes a recessed portion and an elevated portion—to provide high roughness and firm connection.Type: GrantFiled: October 23, 2015Date of Patent: February 14, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Nam-Gyu Baek, Young-Min Lee, Yun-Rae Cho, Sun-Dae Kim
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Publication number: 20160043045Abstract: A pad structure usable with a semiconductor device may include an insulating layer pattern structure, a plug, and a pad. The insulating layer pattern structure has a plug hole and at least one via hole. The plug is formed in the plug hole. The pad is formed on the insulating layer pattern structure. The pad is electrically connected with the plug and has a lower surface and an uneven upper surface. The lower surface includes a protruded portion inserted into the via hole. The uneven upper surface includes a recessed portion and an elevated portion—to provide high roughness and firm connection.Type: ApplicationFiled: October 23, 2015Publication date: February 11, 2016Inventors: Nam-Gyu BAEK, Young-Min LEE, Yun-Rae CHO, Sun-Dae KIM
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Patent number: 9202794Abstract: A pad structure usable with a semiconductor device may include an insulating layer pattern structure, a plug, and a pad. The insulating layer pattern structure has a plug hole and at least one via hole. The plug is formed in the plug hole. The pad is formed on the insulating layer pattern structure. The pad is electrically connected with the plug and has a lower surface and an uneven upper surface. The lower surface includes a protruded portion inserted into the via hole. The uneven upper surface includes a recessed portion and an elevated portion- to provide high roughness and firm connection.Type: GrantFiled: March 14, 2013Date of Patent: December 1, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-Gyu Baek, Young-Min Lee
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Publication number: 20130277833Abstract: A pad structure usable with a semiconductor device may include an insulating layer pattern structure, a plug, and a pad. The insulating layer pattern structure has a plug hole and at least one via hole. The plug is formed in the plug hole. The pad is formed on the insulating layer pattern structure. The pad is electrically connected with the plug and has a lower surface and an uneven upper surface. The lower surface includes a protruded portion inserted into the via hole. The uneven upper surface includes a recessed portion and an elevated portion- to provide high roughness and firm connection.Type: ApplicationFiled: March 14, 2013Publication date: October 24, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Nam-Gyu BAEK, Young-Min LEE