Abstract: According to one general aspect, an apparatus may include a terminal configured to receive an analog input signal. In various embodiments, the apparatus may also include a multistage amplifier configured to amplify the analog input signal by an amount of gain. In some embodiments, the apparatus may include a distributed threshold adjuster interspersed between the stages of the multistage amplifier configured to adjust the DC voltage of the analog input signal to facilitate a decision by an analog-to-digital converter (ADC). In one embodiment, the apparatus may include the ADC configured to convert the amplified analog input signal to a digital output signal.

Abstract: Multiple channel synchronized clock generation scheme. A novel approach is presented herein in which synchronized clock signals are generated that can be used in parallel processing of deserialized signals. When a serial input signal is received, it can be deserialized into a plurality of parallel signals, and each of these parallel signals can be processed at a frequency that is lower than the frequency of the serial signal. Overall, the frequency at which all of the parallel signals are processed can be the same or substantially close to the frequency of the serial signal, so that throughput within a communication system is not compromised or undesirably reduced. This novel approach is operable to perform independent adjustment of the operational parameters within an apparatus that is operable to perform multiple channel synchronized clock generation (e.g., phase rotation and/or division of signals within each of the individual channels can be adjusted independently).

Abstract: Various example embodiments are disclosed. According to one example embodiment, a high bandwidth, fine granularity variable gain amplifier (“VGA”) may comprise an attenuator, a gain block and a gain adjustment control. The attenuator may comprise at least one pair of attenuator differential input nodes and at least one pair of attenuator differential output nodes. The gain block may comprise at least one pair of gain block differential input nodes coupled to the at least one pair of attenuator differential output nodes and at least one pair of gain block differential output nodes. The gain adjustment control may be configured to adjust a gain of the gain block.

Abstract: Various example embodiments are disclosed. According to one example embodiment, a high bandwidth, fine granularity variable gain amplifier (“VGA”) may comprise an attenuator, a gain block and a gain adjustment control. The attenuator may comprise at least one pair of attenuator differential input nodes and at least one pair of attenuator differential output nodes. The gain block may comprise at least one pair of gain block differential input nodes coupled to the at least one pair of attenuator differential output nodes and at least one pair of gain block differential output nodes. The gain adjustment control may be configured to adjust a gain of the gain block.

Abstract: Multiple channel synchronized clock generation scheme. A novel approach is presented herein in which synchronized clock signals are generated that can be used in parallel processing of deserialized signals. When a serial input signal is received, it can be deserialized into a plurality of parallel signals, and each of these parallel signals can be processed at a frequency that is lower than the frequency of the serial signal. Overall, the frequency at which all of the parallel signals are processed can be the same or substantially close to the frequency of the serial signal, so that throughput within a communication system is not compromised or undesirably reduced. This novel approach is operable to perform independent adjustment of the operational parameters within an apparatus that is operable to perform multiple channel synchronized clock generation (e.g., phase rotation and/or division of signals within each of the individual channels can be adjusted independently).

Abstract: An apparatus and method for recovering a clock signal from a Coded Marked Inversion (CMI) encoded signal. A delay and divide circuit receives an incoming CMI encoded signal and produces a signal that has transitions corresponding to the bit boundaries of the CMI signal. This signal is then passed through a clock recovery loop (i.e., a phase-locked loop) to synchronize a clock signal with a CMI signal. The clock recovery loop further includes a delay circuit that adjusts the timing of the feedback signal such that it matches the delay of the CMI signal that occurs as the CMI signal passes through the delay and divide circuit. Accordingly, the circuit adjusts the timing of the recovered clock signal until it matches the clocking of the incoming CMI signal.

Abstract: A phase locked loop circuit and method that substantially decouples control of the phase/frequency and the amplitude of the oscillation output such that the frequency of the oscillation can be controlled independently of the amplitude. The phase locked loop circuit comprises a phase/frequency control loop and an amplitude control loop wherein both loops control an oscillator that oscillates at a certain frequency in response to a phase/frequency control signal generated by the phase/frequency control loop. In addition, the oscillation amplitude is determined by an amplitude control signal generated by the amplitude control loop. As with conventional circuits of this type, a parasitic gain is coupled from the amplitude control loop into the phase/frequency control loop, thereby causing interference between the loops that leads to stability problems.