Patents by Inventor Namik Kocaman
Namik Kocaman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140146922Abstract: Techniques are described herein that provide an interface for receiving and deserializing digital bit stream(s). For instance, a receiver for a high-speed deserializer may include digital slicers, a digital phase interpolator, and a digital clock phase generator. The digital slicers may be configured to determine a digital value of a data input. The digital phase interpolator may be configured to generate an interpolated clock signal based on input clock signals that correspond to respective phases of a reference clock. The phase of the interpolated clock tracks the data input to the receiver through a clock recovery loop. The digital clock phase generator may be configured to generate output clock signals to control timing of the respective digital slicers. The receiver may further include a single digital eye monitor configured to monitor a data eye of the data input.Type: ApplicationFiled: December 19, 2012Publication date: May 29, 2014Applicant: BROADCOM CORPORATIONInventors: Ali Nazemi, Mahmoud Reza Ahmadi, Tamer Ali, Bo Zhang, Mohammed Abdul-Latif, Namik Kocaman, Afshin Momtaz
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Publication number: 20140036982Abstract: Embodiments of the present disclosure enable bandwidth extension of receiver front-end circuits without the use of inductors. As a result, significantly smaller and cheaper receiver implementations are made possible. In an embodiment, bandwidth extension is achieved by virtue of very small floating capacitors that are coupled around amplifier stages of the receiver front-end circuit. Each of the capacitors is configured to generate a negative capacitance for the preceding stage (e.g., equalizer or amplifier), thus extending the bandwidth of the preceding stage. A capacitively-degenerated cross-coupled transistor pair allows bandwidth extension for the final (e.g., amplifier) stage. Embodiments further enable DC offset compensation with the use of a digital feedback loop. The feedback loop can thus be turned on/off as needed, reducing power consumption.Type: ApplicationFiled: August 6, 2012Publication date: February 6, 2014Applicant: Broadcom CorporationInventors: Tamer ALI, Ali Nazemi, Namik Kocaman
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Patent number: 8618964Abstract: According to one general aspect, a distributed threshold adjuster (DTA) may be interspersed between stages of a multistage amplifier to adjust the DC voltage of an input signal. The DTA may include an input signal terminal configured to receive the input signal. The DTA may also include a plurality of current sources configured to produce an adjustment current signal whose amperage is configured to be increased or decreased by fixed steps in order to adjust the DC voltage of the input signal. The DTA may include a control unit configured to selectively turn on or off the individual current sources of the plurality of current sources to select the amperage of the adjustment current signal. The DTA may further include an output terminal configured to produce an output signal, comprising a combination of the input signal and the adjustment current signal, to a stage of a multistage amplifier.Type: GrantFiled: August 11, 2011Date of Patent: December 31, 2013Assignee: Broadcom CorporationInventors: Afshin Momtaz, Namik Kocaman, Bharath Raghavan
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Publication number: 20130285752Abstract: Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal.Type: ApplicationFiled: June 28, 2013Publication date: October 31, 2013Inventors: Mahyar KARGAR, Siavash Fallahi, Namik Kocaman, Mehdi Khanpour, Afshin Momtaz
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Patent number: 8502609Abstract: Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal.Type: GrantFiled: June 10, 2011Date of Patent: August 6, 2013Assignee: Broadcom CorporationInventors: Mahyar Kargar, Siavash Fallahi, Namik Kocaman, Mehdi Khanpour, Afshin Momtaz
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Publication number: 20120313715Abstract: Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal.Type: ApplicationFiled: June 10, 2011Publication date: December 13, 2012Applicant: Broadcom CorporationInventors: Mahyar Kargar, Siavash Fallahi, Namik Kocaman, Mehdi Khanpour, Afshin Momtaz
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Publication number: 20120313714Abstract: Embodiments for reference-less voltage controlled oscillator (VCO) calibration are provided. Embodiments include a VCO calibration module which uses one or more signals from a frequency detector to automatically select a proper VCO band and bring the VCO clock frequency close enough to the data rate. The VCO calibration module uses a calibration code to calibrate the VCO. In embodiments, the calibration code is determined using a frequency search scheme, which includes a discovery phase to determine the proper VCO band, and a binary search phase and a monitoring phase to select the calibration code that brings the VCO clock frequency closest to the data rate.Type: ApplicationFiled: June 10, 2011Publication date: December 13, 2012Applicant: Broadcom CorporationInventors: Mahyar Kargar, Siavash Fallahi, Namik Kocaman, Afshin Momtaz
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Publication number: 20110291757Abstract: According to one general aspect, a distributed threshold adjuster (DTA) may be interspersed between stages of a multistage amplifier to adjust the DC voltage of an input signal. The DTA may include an input signal terminal configured to receive the input signal. The DTA may also include a plurality of current sources configured to produce an adjustment current signal whose amperage is configured to be increased or decreased by fixed steps in order to adjust the DC voltage of the input signal. The DTA may include a control unit configured to selectively turn on or off the individual current sources of the plurality of current sources to select the amperage of the adjustment current signal. The DTA may further include an output terminal configured to produce an output signal, comprising a combination of the input signal and the adjustment current signal, to a stage of a multistage amplifier.Type: ApplicationFiled: August 11, 2011Publication date: December 1, 2011Applicant: BROADCOM CORPRATIONInventors: Afshin Momtaz, Namik Kocaman, Bharath Raghavan
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Patent number: 7973681Abstract: A gating logic receives a non-return-to-zero (NRZ) input signal and couples the NRZ input signal as an NRZ output signal when operating in a NRZ mode of operation and converts the NRZ input signal to a return-to-zero (RZ) output signal when operating in a RZ mode of operation. A circuit coupled to the gating logic receives a clock signal and couples the clock signal to the gating logic to convert the NRZ input signal to the RZ output signal in the RZ mode of operation. In the NRZ mode of operation, the circuit decouples the clock signal and places a predetermined signal state at the gating logic to pass through the NRZ input signal as the NRZ output signal. The circuit receives a select signal to select between the NRZ and RZ modes of operation and the NRZ and RZ modes are obtained by controlling the clock signal to the gating logic.Type: GrantFiled: September 28, 2009Date of Patent: July 5, 2011Assignee: Broadcom CorporationInventors: Adesh Garg, Afshin Momtaz, Namik Kocaman, Delong Cui
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Publication number: 20110074610Abstract: A gating logic receives a non-return-to-zero (NRZ) input signal and couples the NRZ input signal as an NRZ output signal when operating in a NRZ mode of operation and converts the NRZ input signal to a return-to-zero (RZ) output signal when operating in a RZ mode of operation. A circuit coupled to the gating logic receives a clock signal and couples the clock signal to the gating logic to convert the NRZ input signal to the RZ output signal in the RZ mode of operation. In the NRZ mode of operation, the circuit decouples the clock signal and places a predetermined signal state at the gating logic to pass through the NRZ input signal as the NRZ output signal. The circuit receives a select signal to select between the NRZ and RZ modes of operation and the NRZ and RZ modes are obtained by controlling the clock signal to the gating logic.Type: ApplicationFiled: September 28, 2009Publication date: March 31, 2011Applicant: BROADCOM CORPORATIONInventors: Adesh Garg, Afshin Momtaz, Namik Kocaman, Delong Cui
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Publication number: 20100271120Abstract: According to one general aspect, an apparatus may include a terminal configured to receive an analog input signal. In various embodiments, the apparatus may also include a multistage amplifier configured to amplify the analog input signal by an amount of gain. In some embodiments, the apparatus may include a distributed threshold adjuster interspersed between the stages of the multistage amplifier configured to adjust the DC voltage of the analog input signal to facilitate a decision by an analog-to-digital converter (ADC). In one embodiment, the apparatus may include the ADC configured to convert the amplified analog input signal to a digital output signal.Type: ApplicationFiled: October 20, 2009Publication date: October 28, 2010Applicant: Broadcom CorporationInventors: Afshin Momtaz, Namik Kocaman, Bharath Raghavan
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Patent number: 7560986Abstract: A fine granularity, wide-range variable gain amplifier (“VGA”) comprises an attenuator, a high gain signal path, a low gain signal path and a gain adjustment control to adjust a gain of the VGA, wherein the gain adjustment control is configured to cause a selective activation of at least a portion of the low gain signal path or the high gain signal path to achieve a desired overall gain.Type: GrantFiled: March 30, 2007Date of Patent: July 14, 2009Assignee: Broadcom CorporationInventor: Namik Kocaman
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Patent number: 7496133Abstract: An apparatus and method are disclosed to aid a transceiver chip, in a wide-band serial data communications system, in receiving data at multiple data rates. A multi-rate filter within the transceiver chip is implemented as at least one adjustable-rate filter stage and a limiting stage. The at least one adjustable-rate filter stage is used to generate a filtered serial data signal from a received serial data signal. The limiter stage generates a full-swing serial data signal from the filtered serial data signal. A bandwidth of the at least one adjustable-rate filter stage is adjustable in order to receive serial data signals at multiple data rates. The bandwidth of the multi-rate filter within the transceiver chip is selectable by the user of the wide-band communication system.Type: GrantFiled: November 19, 2002Date of Patent: February 24, 2009Assignee: Broadcom CorporationInventors: Ichiro Fujimori, Mario Caresosa, Namik Kocaman
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Publication number: 20080238542Abstract: A fine granularity, wide-range variable gain amplifier (“VGA”) comprises an attenuator, a high gain signal path, a low gain signal path and a gain adjustment control to adjust a gain of the VGA, wherein the gain adjustment control is configured to cause a selective activation of at least a portion of the low gain signal path or the high gain signal path to achieve a desired overall gain.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Inventor: Namik Kocaman
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Patent number: 7391838Abstract: A phase lock loop comprising a plurality of voltage controlled oscillators is presented herein. The phase lock loop can provide a wide range of output frequencies with low jitter. Additionally, the phase lock loop can be incorporated into a clock multiplier unit and a clock and data recovery unit.Type: GrantFiled: May 22, 2003Date of Patent: June 24, 2008Assignee: Broadcom CorporationInventors: Mario Caresosa, Namik Kocaman
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Publication number: 20080130679Abstract: Present herein is a multirate transceiver wherein data can be received at a first data rate and transmitted at a second data rate. The transceiver device comprises a first interface for receiving data at one data rate a mapper that can map data from a first rate to the second rate, and a second interface for transmitting the data at the second data rate.Type: ApplicationFiled: November 1, 2007Publication date: June 5, 2008Inventors: Vikram Natarajan, Kang Xiao, Mario Caresosa, Jay Proano, David Chung, Afshin Momtaz, Randy Stolaruk, Xin Wang, Namik Kocaman
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Patent number: 7324548Abstract: Present herein is a multirate transceiver wherein data can be received at a first data rate and transmitted at a second data rate. The transceiver device comprises a first interface for receiving data at one data rate a mapper that can map data from a first rate to the second rate, and a second interface for transmitting the data at the second data rate.Type: GrantFiled: January 31, 2003Date of Patent: January 29, 2008Assignee: Broadcom CorporationInventors: Vikram Natarajan, Kang Xiao, Mario Caresosa, Jay Proano, David Chung, Afshin Momtaz, Randy Stolaruk, Xin Wang, Namik Kocaman
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Publication number: 20080007340Abstract: A variable gain amplifier including a stage. The stage having a set of switchable differential pairs. The stage providing a gain range to a signal and adjusting a gain of the signal. At least one differential pair in each stage is permanently enabled. The variable gain amplifier may include a plurality of cascaded stages including the stage. In addition, the variable gain amplifier may be adjusted through an interleaved thermometer coding method.Type: ApplicationFiled: September 19, 2007Publication date: January 10, 2008Applicant: BROADCOM CORPORATIONInventors: Namik Kocaman, Afshin Momtaz
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Publication number: 20070241802Abstract: Embodiments of threshold adjustment circuits are disclosed. An example circuit includes a first differential pair of first and second thin oxide transistors. The first and second thin oxide transistors decrease a DC voltage component of a first or second component of an input signal of the circuit. The example circuit further includes a second differential pair of third and fourth thin oxide transistors. The second and third thin oxide transistors increase a DC voltage component of the first or the second component of the input signal. The example circuit also includes a power supply for providing a supply voltage to the circuit, the power supply having a voltage level above a reliability level of the thin oxide transistors. In the example circuit, each of the differential pair thin oxide transistors is switched by a signal that keeps each of the first, second, third, and fourth thin oxide transistors operating in saturation.Type: ApplicationFiled: March 30, 2007Publication date: October 18, 2007Inventors: Namik Kocaman, Afshin Momtaz
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Publication number: 20070188236Abstract: A method and apparatus for an automatic gain control (AGC) loop that utilizes freezing and unfreezing states. A freezing process moves the AGC into a TRANSITION state from a NORMAL state, based on net change of VGA gain control codes over a monitoring time window. The freezing process then moves the AGC into a FROZEN state from the TRANSITION state, based on net change of VGA gain control codes over the monitoring time window. An unfreezing process moves the AGC into the NORMAL state from the FROZEN state, based on signal amplitude changes at the output of the VGA.Type: ApplicationFiled: March 29, 2007Publication date: August 16, 2007Inventors: Namik Kocaman, Afshin Momtaz