Patents by Inventor Namiki YOSHIKAWA

Namiki YOSHIKAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230075852
    Abstract: A semiconductor storage device according to the present embodiment includes a first stack including a plurality of first electrode films stacked in a first direction and electrically isolated from each other and a second stack provided above the first stack and including a plurality of second electrode films stacked in the first direction and electrically isolated from each other. An intermediate film is provided between the first stack and the second stack. A column portion includes a semiconductor layer provided to extend in the first direction in the first and second stacks and in the intermediate film and forms memory cells at an intersection of the semiconductor layer and at least one of the first electrode films and at an intersection of the semiconductor layer and at least one of the second electrode films. The intermediate film includes a silicon oxide film containing nitrogen.
    Type: Application
    Filed: January 20, 2022
    Publication date: March 9, 2023
    Applicant: Kioxia Corporation
    Inventor: Namiki YOSHIKAWA
  • Publication number: 20220077173
    Abstract: A semiconductor memory device includes: a plurality of first conductive layers disposed in a first direction; a structure that includes a first semiconductor layer extending in the first direction and being opposed to the plurality of first conductive layers, agate insulating layer being disposed between the first semiconductor layer and the plurality of first conductive layers, and a second semiconductor layer being contact to one end portion of the first semiconductor layer; a contact connected to the second semiconductor layer; an insulating portion that separates a part of the plurality of first conductive layers in a second direction and is in contact with the structure and the contact from one side in the second direction; and a first insulating layer in contact with the contact from the other side in the second direction. The insulating portion includes an insulating material different from a material of the first insulating layer.
    Type: Application
    Filed: March 2, 2021
    Publication date: March 10, 2022
    Applicant: Kioxia Corporation
    Inventor: Namiki YOSHIKAWA
  • Patent number: 10916557
    Abstract: According to one embodiment, the first electrode layer includes a first portion and a second portion thicker than the first portion. The second electrode layer includes a third portion and a fourth portion thicker than the third portion. The fourth portion is provided on a lower level side of the second portion. The fourth portion has a level difference in a staircase configuration between the fourth portion and the second portion. The fourth portion protrudes along a first direction further than an edge of the second portion. The third electrode layer is provided between the first electrode layer and the third portion. The third electrode layer has an edge receding further than the edge of the second portion of the first electrode layer. The receding is in a reverse direction of a protruding direction of the fourth portion of the second electrode layer.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: February 9, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Shunpei Takeshita, Namiki Yoshikawa, Kazuhide Takamura, Naoki Yamamoto
  • Publication number: 20190348431
    Abstract: According to one embodiment, the first electrode layer includes a first portion and a second portion thicker than the first portion. The second electrode layer includes a third portion and a fourth portion thicker than the third portion. The fourth portion is provided on a lower level side of the second portion. The fourth portion has a level difference in a staircase configuration between the fourth portion and the second portion. The fourth portion protrudes along a first direction further than an edge of the second portion. The third electrode layer is provided between the first electrode layer and the third portion. The third electrode layer has an edge receding further than the edge of the second portion of the first electrode layer. The receding is in a reverse direction of a protruding direction of the fourth portion of the second electrode layer.
    Type: Application
    Filed: September 6, 2018
    Publication date: November 14, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Shunpei TAKESHITA, Namiki YOSHIKAWA, Kazuhide TAKAMURA, Naoki YAMAMOTO