Patents by Inventor Namit Gupta
Namit Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240095547Abstract: An embodiment for monitoring machine learning models to detect and rectify model drift using governance. The embodiment may receive a plurality of machine learning models and register the plurality of machine learning models to a governance dashboard. The embodiment may automatically monitor the received plurality of machine learning models to identify factors used by each of the received plurality of machine learning models and generate corresponding clusters of similar machine learning models. The embodiment may automatically detect an incorrect decision made by a target machine learning model and then automatically calculate a correlation score between the target machine learning model and machine learning models within an associated corresponding cluster of similar machine learning models. The embodiment may, in response to detecting a correlation score above a threshold, automatically determine and output a cluster reinforcement recommendation.Type: ApplicationFiled: September 21, 2022Publication date: March 21, 2024Inventors: Neerju Gupta, Namit Kabra, Yannick Saillet
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Publication number: 20240078241Abstract: An embodiment for managing data using machine learning models and information governance. The embodiment may automatically detect a data analysis request made within a system and identify subject datasets. The embodiment may automatically conduct shallow term assignments on each row and column of data in the subject datasets and automatically match the shallow term assignments for each row and column with a stored set of ranked terms, and automatically flag rows or columns matching with ranked terms above a predetermined threshold ranking for further analysis. The embodiment may automatically and continuously monitor and detect irrelevant metadata types to prevent subsequent analysis and storage of data including the irrelevant metadata types. The embodiment may automatically generate a criticality ranking for stored analysis datasets.Type: ApplicationFiled: September 7, 2022Publication date: March 7, 2024Inventors: Neerju Gupta, Namit Kabra, Yannick Saillet
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Patent number: 11212282Abstract: A method and system directed to performing account activity tracking is provided. More specifically, user activity associated with a user's first account may influence when a user's second account is signed out due to inactivity. Accordingly, an activity request including a first identifier associated with a first user account may be received from a first entity, and based on the first identifier associated with the first user account, a second identifier associated with a second user account may be retrieved, where the first identifier and the second identifier are linked to one another. Activity information for the second identifier associated with the second user account may be obtained which may be provided to the entity. A decision as to whether or not to keep the user signed in may be based on the activity information.Type: GrantFiled: May 15, 2019Date of Patent: December 28, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Akshay Navneetlal Mutha, Namit Gupta, Rohit Dilip Mahale, Alexandra Veronica Rinja
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Publication number: 20200366678Abstract: A method and system directed to performing account activity tracking is provided. More specifically, user activity associated with a user's first account may influence when a user's second account is signed out due to inactivity. Accordingly, an activity request including a first identifier associated with a first user account may be received from a first entity, and based on the first identifier associated with the first user account, a second identifier associated with a second user account may be retrieved, where the first identifier and the second identifier are linked to one another. Activity information for the second identifier associated with the second user account may be obtained which may be provided to the entity. A decision as to whether or not to keep the user signed in may be based on the activity information.Type: ApplicationFiled: May 15, 2019Publication date: November 19, 2020Applicant: Microsoft Technology Licensing, LLCInventors: Akshay Navneetlal MUTHA, Namit GUPTA, Rohit Dilip MAHALE, Alexandra Veronica RINJA
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Patent number: 10715523Abstract: Non-limiting examples of the present disclosure describe generation of a default signed-in state for subsequent authenticated access to a service. Identity provider data for a service is retrieved from any number of identity providers (e.g. a first identity provider and second identity provider). The first and second identity data is evaluated for generation of a default signed-in state to the service. An evaluation determines that at least one of the first identity data and the second identity data comprises data indicating that a user account is signed-in to the service. Data representing the default signed-in state is generated based on a result of the evaluation. The data representing the default signed-in state comprises a selection of one of the first or second identity data that corresponds with the user account that is signed-in to the service. A representation of the service in the default signed-in state may be surfaced.Type: GrantFiled: October 2, 2017Date of Patent: July 14, 2020Assignee: Microsoft Technology Licensing, LLCInventors: Akshay Mutha, Namit Gupta
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Patent number: 10289773Abstract: Information from a circuit design's unified power format (UPF) description is utilized to automate the management of reset domain crossings (RDCs). The UPF description is utilized to identify signals that generate both RDC and power domain crossings (PDCs), thereby allowing a circuit designer to efficiently utilize a common (shared) isolation circuit that functions to manage both the RDC (i.e., during reset functions) and the PDC (i.e., during power management functions). A modified UPF description is introduced that facilitates automated management of RDC issues by treating the reset domains as pseudo-power domains, and utilizing UPF analysis and verification tools to automatically generate both shared and non-shared resources for both RDC and PDC issues.Type: GrantFiled: June 26, 2017Date of Patent: May 14, 2019Assignee: Synopsys, Inc.Inventors: Deep Shah, Namit Gupta, Mohamed Shaker Sarwary
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Publication number: 20190075111Abstract: Non-limiting examples of the present disclosure describe generation of a default signed-in state for subsequent authenticated access to a service. Identity provider data for a service is retrieved from any number of identity providers (e.g. a first identity provider and second identity provider). The first and second identity data is evaluated for generation of a default signed-in state to the service. An evaluation determines that at least one of the first identity data and the second identity data comprises data indicating that a user account is signed-in to the service. Data representing the default signed-in state is generated based on a result of the evaluation. The data representing the default signed-in state comprises a selection of one of the first or second identity data that corresponds with the user account that is signed-in to the service. A representation of the service in the default signed-in state may be surfaced.Type: ApplicationFiled: October 2, 2017Publication date: March 7, 2019Inventors: Akshay Mutha, Namit Gupta
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Patent number: 9886753Abstract: A method for controlling the functional output of a verification tool upon receipt of a circuit description comprises searching for a predetermined base pattern in the circuit description. The method further comprises searching for predetermined sub-patterns that are assigned to the base pattern, in the circuit description. The method further comprises the validation of each found sub-pattern based on a predetermined rule to minimize the set of reported errors that based on verification of the circuit description.Type: GrantFiled: November 12, 2014Date of Patent: February 6, 2018Assignee: Synopsys, Inc.Inventors: Mahantesh Narwade, Namit Gupta, Kaushik De, Rajarshi Mukherjee, Suman Nandan, Subhamoy Pal
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Publication number: 20180004876Abstract: Information from a circuit design's unified power format (UPF) description is utilized to automate the management of reset domain crossings (RDCs). The UPF description is utilized to identify signals that generate both RDC and power domain crossings (PDCs), thereby allowing a circuit designer to efficiently utilize a common (shared) isolation circuit that functions to manage both the RDC (i.e., during reset functions) and the PDC (i.e., during power management functions). A modified UPF description is introduced that facilitates automated management of RDC issues by treating the reset domains as pseudo-power domains, and utilizing UPF analysis and verification tools to automatically generate both shared and non-shared resources for both RDC and PDC issues.Type: ApplicationFiled: June 26, 2017Publication date: January 4, 2018Inventors: Deep Shah, Namit Gupta, Mohamed Shaker Sarwary
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Patent number: 9529948Abstract: A method for functional verification of a circuit description comprises generating a first set of crossover paths based on the circuit description, generating a low power information based on a power design description associated with the circuit description, the low power information determining a set of power state combinations, and generating a second set of crossover paths based on the first set of crossover paths and the low power information, the second set of crossover paths being a subset of the first set of crossover paths. Each of the second set of crossover paths is evaluated to identify circuit description errors, in particular functional circuit description errors.Type: GrantFiled: October 30, 2014Date of Patent: December 27, 2016Assignee: Synopsys, Inc.Inventors: Kaushik De, Mahantesh Narwade, Rajarshi Mukherjee, Namit Gupta
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Publication number: 20150131894Abstract: A method for controlling the functional output of a verification tool upon receipt of a circuit description comprises searching for a predetermined base pattern in the circuit description. The method further comprises searching for predetermined sub-patterns that are assigned to the base pattern, in the circuit description. The method further comprises the validation of each found sub-pattern based on a predetermined rule to minimize the set of reported errors that based on verification of the circuit description.Type: ApplicationFiled: November 12, 2014Publication date: May 14, 2015Inventors: Mahantesh Narwade, Namit Gupta, Kaushik De, Rajarshi Mukherjee, Suman Nandan, Subhamoy Pal
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Publication number: 20150121326Abstract: A method for functional verification of a circuit description comprises generating a first set of crossover paths based on the circuit description, generating a low power information based on a power design description associated with the circuit description, the low power information determining a set of power state combinations, and generating a second set of crossover paths based on the first set of crossover paths and the low power information, the second set of crossover paths being a subset of the first set of crossover paths. Each of the second set of crossover paths is evaluated to identify circuit description errors, in particular functional circuit description errors.Type: ApplicationFiled: October 30, 2014Publication date: April 30, 2015Inventors: Kaushik De, Mahantesh Narwade, Rajarshi Mukherjee, Namit Gupta
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Patent number: 8856706Abstract: A system and methods for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For each of the determined source-to-destination paths, it is determined whether the corresponding source is synchronized. For each source its respective synchronized or unsynchronized result is stored and a report is generated for each source describing whether it is synchronized or unsynchronized. The system may be at least a portion of a computer aided design (CAD) system.Type: GrantFiled: May 6, 2013Date of Patent: October 7, 2014Assignee: Atrenta, Inc.Inventors: Maher Mneimneh, Shaker Sarwary, Paras Mal Jain, Ashish Bansal, Mohammad Movahed-Ezazi, Namit Gupta
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Publication number: 20130246989Abstract: A system and methods for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For each of the determined source-to-destination paths, it is determined whether the corresponding source is synchronized. For each source its respective synchronized or unsynchronized result is stored and a report is generated for each source describing whether it is synchronized or unsynchronized. The system may be at least a portion of a computer aided design (CAD) system.Type: ApplicationFiled: May 6, 2013Publication date: September 19, 2013Applicant: Atrenta, IncInventors: Maher MNEIMNEH, Shaker SARWARY, Paras Mal JAIN, Ashish BANSAL, Mohammad MOVAHED-EZAZI, Namit GUPTA
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Patent number: 8448111Abstract: A method and system for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For each of the determined source-to-destination paths, it is determined whether the corresponding source is synchronized. For each source its respective synchronized or unsynchronized result is stored and a report is generated for each source describing whether it is synchronized or unsynchronized.Type: GrantFiled: January 7, 2011Date of Patent: May 21, 2013Assignee: Atrenta, Inc.Inventors: Maher Mneimneh, Shaker Sarwary, Paras Mal Jain, Ashish Bansal, Mohammad Movahed-Ezazi, Namit Gupta
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Publication number: 20120180015Abstract: A method and system for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For each of the determined source-to-destination paths, it is determined whether the corresponding source is synchronized. For each source its respective synchronized or unsynchronized result is stored and a report is generated for each source describing whether it is synchronized or unsynchronized.Type: ApplicationFiled: January 7, 2011Publication date: July 12, 2012Applicant: ATRENTA, INC.Inventors: Maher MNEIMNEH, Shaker Sarwary, Paras Mal Jain, Ashish Bansal, Mohammad Movahed-Ezazi, Namit Gupta