Patents by Inventor Namit Gupta

Namit Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240095547
    Abstract: An embodiment for monitoring machine learning models to detect and rectify model drift using governance. The embodiment may receive a plurality of machine learning models and register the plurality of machine learning models to a governance dashboard. The embodiment may automatically monitor the received plurality of machine learning models to identify factors used by each of the received plurality of machine learning models and generate corresponding clusters of similar machine learning models. The embodiment may automatically detect an incorrect decision made by a target machine learning model and then automatically calculate a correlation score between the target machine learning model and machine learning models within an associated corresponding cluster of similar machine learning models. The embodiment may, in response to detecting a correlation score above a threshold, automatically determine and output a cluster reinforcement recommendation.
    Type: Application
    Filed: September 21, 2022
    Publication date: March 21, 2024
    Inventors: Neerju Gupta, Namit Kabra, Yannick Saillet
  • Publication number: 20240078241
    Abstract: An embodiment for managing data using machine learning models and information governance. The embodiment may automatically detect a data analysis request made within a system and identify subject datasets. The embodiment may automatically conduct shallow term assignments on each row and column of data in the subject datasets and automatically match the shallow term assignments for each row and column with a stored set of ranked terms, and automatically flag rows or columns matching with ranked terms above a predetermined threshold ranking for further analysis. The embodiment may automatically and continuously monitor and detect irrelevant metadata types to prevent subsequent analysis and storage of data including the irrelevant metadata types. The embodiment may automatically generate a criticality ranking for stored analysis datasets.
    Type: Application
    Filed: September 7, 2022
    Publication date: March 7, 2024
    Inventors: Neerju Gupta, Namit Kabra, Yannick Saillet
  • Patent number: 11212282
    Abstract: A method and system directed to performing account activity tracking is provided. More specifically, user activity associated with a user's first account may influence when a user's second account is signed out due to inactivity. Accordingly, an activity request including a first identifier associated with a first user account may be received from a first entity, and based on the first identifier associated with the first user account, a second identifier associated with a second user account may be retrieved, where the first identifier and the second identifier are linked to one another. Activity information for the second identifier associated with the second user account may be obtained which may be provided to the entity. A decision as to whether or not to keep the user signed in may be based on the activity information.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: December 28, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Akshay Navneetlal Mutha, Namit Gupta, Rohit Dilip Mahale, Alexandra Veronica Rinja
  • Publication number: 20200366678
    Abstract: A method and system directed to performing account activity tracking is provided. More specifically, user activity associated with a user's first account may influence when a user's second account is signed out due to inactivity. Accordingly, an activity request including a first identifier associated with a first user account may be received from a first entity, and based on the first identifier associated with the first user account, a second identifier associated with a second user account may be retrieved, where the first identifier and the second identifier are linked to one another. Activity information for the second identifier associated with the second user account may be obtained which may be provided to the entity. A decision as to whether or not to keep the user signed in may be based on the activity information.
    Type: Application
    Filed: May 15, 2019
    Publication date: November 19, 2020
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Akshay Navneetlal MUTHA, Namit GUPTA, Rohit Dilip MAHALE, Alexandra Veronica RINJA
  • Patent number: 10715523
    Abstract: Non-limiting examples of the present disclosure describe generation of a default signed-in state for subsequent authenticated access to a service. Identity provider data for a service is retrieved from any number of identity providers (e.g. a first identity provider and second identity provider). The first and second identity data is evaluated for generation of a default signed-in state to the service. An evaluation determines that at least one of the first identity data and the second identity data comprises data indicating that a user account is signed-in to the service. Data representing the default signed-in state is generated based on a result of the evaluation. The data representing the default signed-in state comprises a selection of one of the first or second identity data that corresponds with the user account that is signed-in to the service. A representation of the service in the default signed-in state may be surfaced.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: July 14, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Akshay Mutha, Namit Gupta
  • Patent number: 10289773
    Abstract: Information from a circuit design's unified power format (UPF) description is utilized to automate the management of reset domain crossings (RDCs). The UPF description is utilized to identify signals that generate both RDC and power domain crossings (PDCs), thereby allowing a circuit designer to efficiently utilize a common (shared) isolation circuit that functions to manage both the RDC (i.e., during reset functions) and the PDC (i.e., during power management functions). A modified UPF description is introduced that facilitates automated management of RDC issues by treating the reset domains as pseudo-power domains, and utilizing UPF analysis and verification tools to automatically generate both shared and non-shared resources for both RDC and PDC issues.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: May 14, 2019
    Assignee: Synopsys, Inc.
    Inventors: Deep Shah, Namit Gupta, Mohamed Shaker Sarwary
  • Publication number: 20190075111
    Abstract: Non-limiting examples of the present disclosure describe generation of a default signed-in state for subsequent authenticated access to a service. Identity provider data for a service is retrieved from any number of identity providers (e.g. a first identity provider and second identity provider). The first and second identity data is evaluated for generation of a default signed-in state to the service. An evaluation determines that at least one of the first identity data and the second identity data comprises data indicating that a user account is signed-in to the service. Data representing the default signed-in state is generated based on a result of the evaluation. The data representing the default signed-in state comprises a selection of one of the first or second identity data that corresponds with the user account that is signed-in to the service. A representation of the service in the default signed-in state may be surfaced.
    Type: Application
    Filed: October 2, 2017
    Publication date: March 7, 2019
    Inventors: Akshay Mutha, Namit Gupta
  • Patent number: 9886753
    Abstract: A method for controlling the functional output of a verification tool upon receipt of a circuit description comprises searching for a predetermined base pattern in the circuit description. The method further comprises searching for predetermined sub-patterns that are assigned to the base pattern, in the circuit description. The method further comprises the validation of each found sub-pattern based on a predetermined rule to minimize the set of reported errors that based on verification of the circuit description.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: February 6, 2018
    Assignee: Synopsys, Inc.
    Inventors: Mahantesh Narwade, Namit Gupta, Kaushik De, Rajarshi Mukherjee, Suman Nandan, Subhamoy Pal
  • Publication number: 20180004876
    Abstract: Information from a circuit design's unified power format (UPF) description is utilized to automate the management of reset domain crossings (RDCs). The UPF description is utilized to identify signals that generate both RDC and power domain crossings (PDCs), thereby allowing a circuit designer to efficiently utilize a common (shared) isolation circuit that functions to manage both the RDC (i.e., during reset functions) and the PDC (i.e., during power management functions). A modified UPF description is introduced that facilitates automated management of RDC issues by treating the reset domains as pseudo-power domains, and utilizing UPF analysis and verification tools to automatically generate both shared and non-shared resources for both RDC and PDC issues.
    Type: Application
    Filed: June 26, 2017
    Publication date: January 4, 2018
    Inventors: Deep Shah, Namit Gupta, Mohamed Shaker Sarwary
  • Patent number: 9529948
    Abstract: A method for functional verification of a circuit description comprises generating a first set of crossover paths based on the circuit description, generating a low power information based on a power design description associated with the circuit description, the low power information determining a set of power state combinations, and generating a second set of crossover paths based on the first set of crossover paths and the low power information, the second set of crossover paths being a subset of the first set of crossover paths. Each of the second set of crossover paths is evaluated to identify circuit description errors, in particular functional circuit description errors.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: December 27, 2016
    Assignee: Synopsys, Inc.
    Inventors: Kaushik De, Mahantesh Narwade, Rajarshi Mukherjee, Namit Gupta
  • Publication number: 20150131894
    Abstract: A method for controlling the functional output of a verification tool upon receipt of a circuit description comprises searching for a predetermined base pattern in the circuit description. The method further comprises searching for predetermined sub-patterns that are assigned to the base pattern, in the circuit description. The method further comprises the validation of each found sub-pattern based on a predetermined rule to minimize the set of reported errors that based on verification of the circuit description.
    Type: Application
    Filed: November 12, 2014
    Publication date: May 14, 2015
    Inventors: Mahantesh Narwade, Namit Gupta, Kaushik De, Rajarshi Mukherjee, Suman Nandan, Subhamoy Pal
  • Publication number: 20150121326
    Abstract: A method for functional verification of a circuit description comprises generating a first set of crossover paths based on the circuit description, generating a low power information based on a power design description associated with the circuit description, the low power information determining a set of power state combinations, and generating a second set of crossover paths based on the first set of crossover paths and the low power information, the second set of crossover paths being a subset of the first set of crossover paths. Each of the second set of crossover paths is evaluated to identify circuit description errors, in particular functional circuit description errors.
    Type: Application
    Filed: October 30, 2014
    Publication date: April 30, 2015
    Inventors: Kaushik De, Mahantesh Narwade, Rajarshi Mukherjee, Namit Gupta
  • Patent number: 8856706
    Abstract: A system and methods for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For each of the determined source-to-destination paths, it is determined whether the corresponding source is synchronized. For each source its respective synchronized or unsynchronized result is stored and a report is generated for each source describing whether it is synchronized or unsynchronized. The system may be at least a portion of a computer aided design (CAD) system.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: October 7, 2014
    Assignee: Atrenta, Inc.
    Inventors: Maher Mneimneh, Shaker Sarwary, Paras Mal Jain, Ashish Bansal, Mohammad Movahed-Ezazi, Namit Gupta
  • Publication number: 20130246989
    Abstract: A system and methods for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For each of the determined source-to-destination paths, it is determined whether the corresponding source is synchronized. For each source its respective synchronized or unsynchronized result is stored and a report is generated for each source describing whether it is synchronized or unsynchronized. The system may be at least a portion of a computer aided design (CAD) system.
    Type: Application
    Filed: May 6, 2013
    Publication date: September 19, 2013
    Applicant: Atrenta, Inc
    Inventors: Maher MNEIMNEH, Shaker SARWARY, Paras Mal JAIN, Ashish BANSAL, Mohammad MOVAHED-EZAZI, Namit GUPTA
  • Patent number: 8448111
    Abstract: A method and system for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For each of the determined source-to-destination paths, it is determined whether the corresponding source is synchronized. For each source its respective synchronized or unsynchronized result is stored and a report is generated for each source describing whether it is synchronized or unsynchronized.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: May 21, 2013
    Assignee: Atrenta, Inc.
    Inventors: Maher Mneimneh, Shaker Sarwary, Paras Mal Jain, Ashish Bansal, Mohammad Movahed-Ezazi, Namit Gupta
  • Publication number: 20120180015
    Abstract: A method and system for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For each of the determined source-to-destination paths, it is determined whether the corresponding source is synchronized. For each source its respective synchronized or unsynchronized result is stored and a report is generated for each source describing whether it is synchronized or unsynchronized.
    Type: Application
    Filed: January 7, 2011
    Publication date: July 12, 2012
    Applicant: ATRENTA, INC.
    Inventors: Maher MNEIMNEH, Shaker Sarwary, Paras Mal Jain, Ashish Bansal, Mohammad Movahed-Ezazi, Namit Gupta