Patents by Inventor Namit Varma

Namit Varma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230195162
    Abstract: Distribution of a reset signal across a system-on-chip (SoC) may be the highest latency signal in the circuit. As a result, the operating frequency of the device is reduced to ensure that the reset signal reaches all intellectual property (IP) blocks during a single clock cycle. A reset synchronizer receives the clock signal and the reset signal as inputs and generates a synchronous reset signal as an output. The synchronous reset signal has a fixed timing relationship with the clock signal. The clock signal may be paused when a reset signal is received. As a result, distribution of the synchronous reset signal may be performed without regard to the latency of the signal. After the synchronous reset signal has been received by all of the IP blocks, reset is deasserted and the clock signal is resumed.
    Type: Application
    Filed: February 10, 2023
    Publication date: June 22, 2023
    Inventors: Namit Varma, Sarma Jonnavithula, Mohan Krishna Vedam, Christopher C. LaFrieda, Virantha N. Ekanayake
  • Patent number: 11681324
    Abstract: Distribution of a reset signal across a system-on-chip (SoC) may be the highest latency signal in the circuit. As a result, the operating frequency of the device is reduced to ensure that the reset signal reaches all intellectual property (IP) blocks during a single clock cycle. A reset synchronizer receives the clock signal and the reset signal as inputs and generates a synchronous reset signal as an output. The synchronous reset signal has a fixed timing relationship with the clock signal. The clock signal may be paused when a reset signal is received. As a result, distribution of the synchronous reset signal may be performed without regard to the latency of the signal. After the synchronous reset signal has been received by all of the IP blocks, reset is deasserted and the clock signal is resumed.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: June 20, 2023
    Assignee: Achronix Semiconductor Corporation
    Inventors: Namit Varma, Sarma Jonnavithula, Mohan Krishna Vedam, Christopher C. LaFrieda, Virantha N. Ekanayake
  • Publication number: 20230106841
    Abstract: Distribution of a reset signal across a system-on-chip (SoC) may be the highest latency signal in the circuit. As a result, the operating frequency of the device is reduced to ensure that the reset signal reaches all intellectual property (IP) blocks during a single clock cycle. A reset synchronizer receives the clock signal and the reset signal as inputs and generates a synchronous reset signal as an output. The synchronous reset signal has a fixed timing relationship with the clock signal. The clock signal may be paused when a reset signal is received. As a result, distribution of the synchronous reset signal may be performed without regard to the latency of the signal. After the synchronous reset signal has been received by all of the IP blocks, reset is deasserted and the clock signal is resumed.
    Type: Application
    Filed: October 1, 2021
    Publication date: April 6, 2023
    Inventors: Namit Varma, Sarma Jonnavithula, Mohan Krishna Vedam, Christopher C. LaFrieda, Virantha N. Ekanayake
  • Patent number: 10831959
    Abstract: An advanced timing mode has a path that originates from a host application-specific integrated circuit (ASIC) and terminates at a register inside an embedded field programmable gate array (FPGA), bypassing interface cluster registers. The terminating register may be present at a boundary between the host ASIC and the embedded FPGA or deep inside the embedded FPGA. In a clock trunk input with internal divergence timing scenario, a clock output from a phase-locked loop (PLL) in the host ASIC is driven through a clock trunk into the embedded FPGA and, from there, diverges into interface cluster registers and the boundary adjacent to the host ASIC. A clock trunk input with external divergence timing scenario is similar to the internal divergence scenario except that a clock divergence occurs before the clock enters a clock trunk of the embedded FPGA. In a boundary clock input scenario, a PLL drives both the host ASIC and the embedded FPGA interface clusters.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: November 10, 2020
    Assignee: Achronix Semiconductor Corporation
    Inventors: Namit Varma, Shirish Jawale
  • Publication number: 20200311219
    Abstract: An advanced timing mode has a path that originates from a host application-specific integrated circuit (ASIC) and terminates at a register inside an embedded field programmable gate array (FPGA), bypassing interface cluster registers. The terminating register may be present at a boundary between the host ASIC and the embedded FPGA or deep inside the embedded FPGA. In a clock trunk input with internal divergence timing scenario, a clock output from a phase-locked loop (PLL) in the host AMC is driven through a clock trunk into the embedded FPGA and, from there, diverges into interface cluster registers and the boundary adjacent to the host ASIC. A clock trunk input with external divergence timing scenario is similar to the internal divergence scenario except that a clock divergence occurs before the clock enters a clock trunk of the embedded FPGA. In a boundary clock input scenario, a PLL drives both the host ASIC and the embedded FPGA interface clusters.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 1, 2020
    Inventors: Namit Varma, Shirish Jawale