Patents by Inventor Namita Joshi

Namita Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory system performance configuration
    Patent number: 9442842
    Abstract: A nonvolatile memory die is tested to determine certain parameters such as read time, which are then recorded in the nonvolatile memory die. After the die is incorporated into a memory system, and firmware is downloaded, the nonvolatile memory system uses the recorded parameters to determine how to configure the memory system for operation within specified limits, such as determining how much delay to apply to read operations.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: September 13, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Preeti Yadav, Barys Sarana, Abhijeet Bhalerao, Frederick Fernandez, Namita Joshi
  • Memory System Performance Configuration
    Publication number: 20150052289
    Abstract: A nonvolatile memory die is tested to determine certain parameters such as read time, which are then recorded in the nonvolatile memory die. After the die is incorporated into a memory system, and firmware is downloaded, the nonvolatile memory system uses the recorded parameters to determine how to configure the memory system for operation within specified limits, such as determining how much delay to apply to read operations.
    Type: Application
    Filed: August 19, 2013
    Publication date: February 19, 2015
    Applicant: SanDisk Technologies, Inc.
    Inventors: Preeti Yadav, Barys Sarana, Abhijeet Bhalerao, Frederick Fernandez, Namita Joshi
  • General frame-based compression method
    Patent number: 6154155
    Abstract: A method of coding and compressing telemetry data makes use of the fact that the telemetry frames are typically highly correlated at a distance, .delta., corresponding to commutation or data periodicities. The existence of such periodicity is used to render a portion of each frame to zeros. The next steps are to search for and remove correlations between the bits in a set of frames, denoted {F.sub.i *}. The compression algorithm implementing the method according to the invention has four sub-steps; Data preconditioning, Compression and coding of first frame, F.sub.1, Compression and coding of frames 2-.delta., F.sub.1 -F.sub..delta., and Compression and coding of F.sub..delta.+1 and on, the steady-state mode.
    Type: Grant
    Filed: March 8, 1999
    Date of Patent: November 28, 2000
    Assignee: General Electric Company
    Inventors: John Erik Hershey, Namita Joshi, Mark Lewis Grabb, John Anderson Fergus Ross, Thomas Gerard Nowak, Vincent Paul Staudinger