Patents by Inventor Namkyu Edward CHO
Namkyu Edward CHO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230207628Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.Type: ApplicationFiled: March 1, 2023Publication date: June 29, 2023Inventors: Namkyu Edward CHO, Seung Soo HONG, Geum Jung SEONG, Seung Hun LEE, Jeong Yun LEE
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Patent number: 11600698Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.Type: GrantFiled: December 11, 2020Date of Patent: March 7, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Namkyu Edward Cho, Seung Soo Hong, Geum Jung Seong, Seung Hun Lee, Jeong Yun Lee
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Patent number: 11508751Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.Type: GrantFiled: January 8, 2021Date of Patent: November 22, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Namkyu Edward Cho, Seok Hoon Kim, Myung Il Kang, Geo Myung Shin, Seung Hun Lee, Jeong Yun Lee, Min Hee Choi, Jeong Min Choi
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Publication number: 20210159246Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.Type: ApplicationFiled: January 8, 2021Publication date: May 27, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Namkyu Edward CHO, Seok Hoon KIM, Myung Il KANG, Geo Myung SHIN, Seung Hun LEE, Jeong Yun LEE, Min Hee CHOI, Jeong Min CHOI
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Publication number: 20210098577Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.Type: ApplicationFiled: December 11, 2020Publication date: April 1, 2021Inventors: Namkyu Edward Cho, Seung Soo Hong, Geum Jung Seong, Seung Hun Lee, Jeong Yun Lee
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Patent number: 10930668Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.Type: GrantFiled: February 11, 2019Date of Patent: February 23, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Namkyu Edward Cho, Seok Hoon Kim, Myung Ii Kang, Geo Myung Shin, Seung Hun Lee, Jeong Yun Lee, Min Hee Choi, Jeong Min Choi
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Patent number: 10896957Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.Type: GrantFiled: May 30, 2018Date of Patent: January 19, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Namkyu Edward Cho, Seung Soo Hong, Geum Jung Seong, Seung Hun Lee, Jeong Yun Lee
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Publication number: 20200027895Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.Type: ApplicationFiled: February 11, 2019Publication date: January 23, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Namkyu Edward CHO, Seok Hoon KIM, Myung II KANG, Geo Myung SHIN, Seung Hun LEE, Jeong Yun LEE, Min Hee CHOI, Jeong Min CHOI
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Publication number: 20190288065Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.Type: ApplicationFiled: May 30, 2018Publication date: September 19, 2019Inventors: Namkyu Edward CHO, Seung Soo HONG, Geum Jung SEONG, Seung Hun LEE, Jeong Yun LEE