Patents by Inventor Namratha Jaisimha

Namratha Jaisimha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DATA ORDERING IN A MULTI-NODE SYSTEM
    Publication number: 20090006712
    Abstract: Methods and apparatuses for data ordering in a multi-node system that supports non-snoop memory transactions.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 1, 2009
    Inventors: FATMA EHSAN, Binata Bhattacharyya, Namratha Jaisimha, Liang Yin
  • METHODS AND APPARATUS TO CONTROL POWER CONSUMPTION WITHIN A PROCESSOR
    Publication number: 20070234094
    Abstract: Methods and apparatus are disclosed to control power consumption within a processor. An example apparatus disclosed herein includes logic to identify at least one instruction type and to initialize a counter value corresponding to a maximum number of instructions to be performed, the maximum number being at least partially dependent upon the identified at least one instruction type. The example apparatus also includes processing logic to be enabled or disabled based, at least in part, on the counter value.
    Type: Application
    Filed: June 7, 2007
    Publication date: October 4, 2007
    Inventors: Nicholas Samra, Andrew Huang, Namratha Jaisimha
  • Methods and apparatus to control power consumption within a processor
    Publication number: 20050138335
    Abstract: Methods and apparatus are disclosed to control power consumption within a processor. An example processor disclosed herein comprises an instruction retirement unit; a first set of functional blocks to process a first set of instructions having a first instruction type; a second set of functional blocks to process a second set of instructions having a second instruction type; and a controller to enable the first set of functional blocks to process an instruction allocated to the instruction retirement unit if the type of the instruction is the first type, and to disable the first set of functional blocks after the instruction is retired by the instruction retirement unit.
    Type: Application
    Filed: December 23, 2003
    Publication date: June 23, 2005
    Inventors: Nicholas Samra, Andrew Huang, Namratha Jaisimha
  • Return address stack including speculative return address buffer with back pointers
    Patent number: 6898699
    Abstract: An apparatus for storing predicted return addresses of instructions being executed by a pipelined processor, the apparatus includes a two part return address buffer that includes a speculative return address buffer and a committed return address buffer, both of which having multiple entries that may include predicted return addresses that have been pushed onto the return buffer.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: May 24, 2005
    Assignee: Intel Corporation
    Inventors: Stephan J. Jourdan, John Alan Miller, Namratha Jaisimha
  • Return address stack
    Publication number: 20030120906
    Abstract: An apparatus for storing predicted return addresses of instructions being executed by a pipelined processor, the apparatus includes a two part return address buffer that includes a speculative return address buffer and a committed return address buffer, both of which having multiple entries that may include predicted return addresses that have been pushed onto the return buffer.
    Type: Application
    Filed: December 21, 2001
    Publication date: June 26, 2003
    Inventors: Stephan J. Jourdan, John Alan Miller, Namratha Jaisimha