Patents by Inventor Namratha Rajasekharaiah Jaisimha

Namratha Rajasekharaiah Jaisimha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Recovery mechanism for L1 data cache parity errors
    Patent number: 6332181
    Abstract: A method of handling a cache error (such as a parity error), which allows a software recovery, by reporting the error using an unrelated system resource, such as an interrupt service, and particularly a data storage interrupt. The parity error can be reported by generating a data storage interrupt and using the data storage interrupt status register (DSISR) to indicate that the data storage interrupt is a result of the parity error. The context of the processor can be fully synchronized while handling the parity error.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: December 18, 2001
    Assignee: International Business Machines Corporation
    Inventors: Douglas Craig Bossen, Kevin Arthur Chiarot, Namratha Rajasekharaiah Jaisimha, Avijit Saha