Abstract: Disclosed herein are an apparatus and method for receiving a signal based on FTN. The apparatus for receiving a signal based on FTN includes an equalizer for creating a Log Likelihood Ratio (LLR) sequence by equalizing an FTN signal sequence sampled at an FTN signaling rate; a deinterleaver for deinterleaving the created LLR sequence; a decoder for decoding the LLR sequence by correcting errors in the deinterleaved LLR sequence; an interleaver for interleaving the decoded LLR sequence and providing the interleaved LLR sequence to the equalizer; and an FTN interference estimation unit for providing the FTN signal sequence, from which an FTN interference sequence is eliminated, to the equalizer, using the interleaved LLR sequence.

Abstract: Disclosed herein are an apparatus and method for receiving a signal based on FTN. The apparatus for receiving a signal based on FTN includes an equalizer for creating a Log Likelihood Ratio (LLR) sequence by equalizing an FTN signal sequence sampled at an FTN signaling rate; a deinterleaver for deinterleaving the created LLR sequence; a decoder for decoding the LLR sequence by correcting errors in the deinterleaved LLR sequence; an interleaver for interleaving the decoded LLR sequence and providing the interleaved LLR sequence to the equalizer; and an FTN interference estimation unit for providing the FTN signal sequence, from which an FTN interference sequence is eliminated, to the equalizer, using the interleaved LLR sequence.

Abstract: A method of operating a memory controller includes; receiving hard decision data and first soft decision data from a non-volatile memory device, performing a first ECC decoding operation using the hard decision data and the first soft decision data: and then determining a second soft decision read voltage or reclaim operation of the non-volatile memory device based on the number of iteration operation of the first ECC (error correction code).

Abstract: A method of performing a cyclic redundancy check (CRC) operation in a memory system, and a memory controller that uses the same. The method includes initializing a linear feed-back shift register (LFSR) circuit in a CRC polynomial, generating CRC parity information with respect to input data to be stored in a memory device by using the LFSR circuit, and generating a CRC code with respect to the input data based on the CRC parity information, such that the initialization of the LFSR circuit is set such that a register initial value of the LFSR circuit is determined to satisfy a condition that, when data input to the LFSR circuit is first state information, the CRC parity information generated from the LFSR circuit is second state information.

Abstract: A hard-decision decoding method includes performing operations necessary for first updating of a check node while loading data, which is input to a decoder, to an input buffer; first updating the check node by using a result of the performing of the operations after storing data, corresponding to one codeword, to the input buffer; and performing low-density parity check (LDPC) decoding by using a result of the first updating of the check node.

Abstract: A method of operating a memory controller includes; receiving hard decision data and first soft decision data from a non-volatile memory device, performing a first ECC decoding operation using the hard decision data and the first soft decision data: and then determining a second soft decision read voltage or reclaim operation of the non-volatile memory device based on the number of iteration operation of the first ECC (error correction code).

Abstract: A method of performing a cyclic redundancy check (CRC) operation in a memory system, and a memory controller that uses the same. The method includes initializing a linear feed-back shift register (LFSR) circuit in a CRC polynomial, generating CRC parity information with respect to input data to be stored in a memory device by using the LFSR circuit, and generating a CRC code with respect to the input data based on the CRC parity information, such that the initialization of the LFSR circuit is set such that a register initial value of the LFSR circuit is determined to satisfy a condition that, when data input to the LFSR circuit is first state information, the CRC parity information generated from the LFSR circuit is second state information.

Abstract: A hard-decision decoding method includes performing operations necessary for first updating of a check node while loading data, which is input to a decoder, to an input buffer; first updating the check node by using a result of the performing of the operations after storing data, corresponding to one codeword, to the input buffer; and performing low-density parity check (LDPC) decoding by using a result of the first updating of the check node.

Abstract: Provided are a network-coding apparatus and method which can increase a data communication capacity in a communication environment to which an error-correction code (ECC) is applied. The network-coding apparatus includes a received signal processing unit receiving at least two signals, and decoding the at least two received signals; and a transmission signal processing unit receiving the at least two decoded signals from the received signal processing unit, merging the at least two decoded signals, and generating a merged transmission signal.

Abstract: Provided is a fine frequency synchronization method of a WiBro system, and particularly, a fine frequency synchronization method which measures a spread degree of a received signal of an adjacent subcarrier using orthogonality of PN sequences and thereby estimates a frequency offset, in a base station or a wireless repeater without using a GPS receiver. The fine frequency synchronization method includes: (a) performing despreading on received adjacent subcarrier sequences, using a PN sequence transmitted from a transmitting party; (b) obtaining ratios of correlative values obtained by the despreading; and (c) estimating a frequency offset on the basis of the ratio of correlative values. Accordingly, fine frequency offset estimation with relatively low complexity is possible without using a GPS receiver in a WiBro environment where interference signals of other base stations or repeaters exist.

Abstract: Provided are a network-coding apparatus and method which can increase a data communication capacity in a communication environment to which an error-correction code (ECC) is applied. The network-coding apparatus includes a received signal processing unit receiving at least two signals, and decoding the at least two received signals; and a transmission signal processing unit receiving the at least two decoded signals from the received signal processing unit, merging the at least two decoded signals, and generating a merged transmission signal.

Abstract: Provided is a fine frequency synchronization method of a WiBro system, and particularly, a fine frequency synchronization method which measures a spread degree of a received signal of an adjacent subcarrier using orthogonality of PN sequences and thereby estimates a frequency offset, in a base station or a wireless repeater without using a GPS receiver. The fine frequency synchronization method includes: (a) performing despreading on received adjacent subcarrier sequences, using a PN sequence transmitted from a transmitting party; (b) obtaining ratios of correlative values obtained by the despreading; and (c) estimating a frequency offset on the basis of the ratio of correlative values. Accordingly, fine frequency offset estimation with relatively low complexity is possible without using a GPS receiver in a WiBro environment where interference signals of other base stations or repeaters exist.

Abstract: Disclosed are an apparatus and a method for reducing the coding complexity in an LDPC code used in a digital communication system. In the method, parameters required for coding are determined according to a coding rate and a code length, a seed matrix is generated according to values of the parameters, a plurality of cell matrices are generated according to the values of the parameters, a parity check matrix is generated using the seed matrix and the cell matrix, and information bits are coded from the parity check matrix. The method can be realized by a small memory and a simple shift register and can perform coding even without obtaining a generation matrix, thereby remarkably reducing the complexity of a system.

Abstract: An apparatus is provided for detecting a signal in a communication system using a Multiple Input Multiple Output (MIMO) scheme. The signal detection apparatus includes a detector for generating second matrixes by extending a first matrix composed of channel response vectors, generating specific matrixes by decomposing the second matrixes, generating a lattice point of vectors constituting the second matrixes, estimating a signal using the generated specific matrixes and lattice point, and detecting the estimated signal as a received signal if the estimated signal has a value within a predetermined allowable range.

Abstract: A method for generating a parity check matrix of a Low Density Parity Check (LDPC) code. A base matrix is generated in which elements with a value of 1 are arranged at predefined distances. The elements with the value of 1 in the base matrix are replaced with predefined sub-matrices. The method can improve the performance of the LDPC code by implementing the parity check matrix in which the number of 4-cycles or 6-cycles adversely affecting the LDPC code performance is minimized.

Abstract: Disclosed are an apparatus and a method for reducing the coding complexity in an LDPC code used in a digital communication system. In the method, parameters required for coding are determined according to a coding rate and a code length, a seed matrix is generated according to values of the parameters, a plurality of cell matrices are generated according to the values of the parameters, a parity check matrix is generated using the seed matrix and the cell matrix, and information bits are coded from the parity check matrix. The method can be realized by a small memory and a simple shift register and can perform coding even without obtaining a generation matrix, thereby remarkably reducing the complexity of a system.