Patents by Inventor Nan-Cheng Chen

Nan-Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210202425
    Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor device bonded to a base through a first conductive structure. The semiconductor device includes a carrier substrate including a conductive trace. A portion of the conductive trace is elongated. The semiconductor device also includes a second conductive structure above the carrier substrate. A portion of the second conductive structure is in contact with the portion of the conductive trace. The semiconductor device further includes a semiconductor body mounted above the conductive trace. The semiconductor body is connected to the second conductive structure.
    Type: Application
    Filed: March 11, 2021
    Publication date: July 1, 2021
    Applicant: MediaTek Inc.
    Inventors: Che-Ya Chou, Wen-Sung Hsu, Nan-Cheng Chen
  • Publication number: 20210193540
    Abstract: A semiconductor device includes a substrate, a body structure and an electronic component. The body structure is disposed above the substrate and includes a semiconductor die, a molding compound, a conductive component and a lower redistribution layer (RDL). The semiconductor die has an active surface. The molding compound encapsulates the semiconductor die and has a lower surface, an upper surface opposite to the lower surface and a through hole extending to the upper surface from the lower surface. The conductive component is formed within the through hole. The lower RDL is formed on the lower surface of the molding compound, the active surface of the semiconductor die and the conductive component exposed from the lower surface. The electronic component is disposed above the upper surface of the molding compound and electrically connected to the lower RDL through the conductive component.
    Type: Application
    Filed: March 3, 2021
    Publication date: June 24, 2021
    Applicant: MediaTek Inc.
    Inventors: Nan-Cheng Chen, Che-Ya Chou, Hsing-Chih Liu, Che-Hung Kuo
  • Patent number: 10991669
    Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor device bonded to a base through a first conductive structure. The semiconductor device includes a carrier substrate including a conductive trace. A portion of the conductive trace is elongated. The semiconductor device also includes a second conductive structure above the carrier substrate. A portion of the second conductive structure is in contact with the portion of the conductive trace. The semiconductor device further includes a semiconductor body mounted above the conductive trace. The semiconductor body is connected to the second conductive structure.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: April 27, 2021
    Assignee: MediaTek Inc.
    Inventors: Che-Ya Chou, Wen-Sung Hsu, Nan-Cheng Chen
  • Publication number: 20210036405
    Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.
    Type: Application
    Filed: October 20, 2020
    Publication date: February 4, 2021
    Applicant: MediaTek Inc.
    Inventors: Fu-Yi Han, Che-Ya Chou, Che-Hung Kuo, Wen-Chou Wu, Nan-Cheng Chen, Min-Chen Lin, Hsing-Chih Liu
  • Publication number: 20200381365
    Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.
    Type: Application
    Filed: August 17, 2020
    Publication date: December 3, 2020
    Inventors: Wen-Sung HSU, Tao CHENG, Nan-Cheng CHEN, Che-Ya CHOU, Wen-Chou WU, Yen-Ju LU, Chih-Ming HUNG, Wei-Hsiu HSU
  • Patent number: 10847869
    Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: November 24, 2020
    Assignee: MediaTek Inc.
    Inventors: Fu-Yi Han, Che-Ya Chou, Che-Hung Kuo, Wen-Chou Wu, Nan-Cheng Chen, Min-Chen Lin, Hsing-Chih Liu
  • Patent number: 10784206
    Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure and a first antenna layer. The first antenna layer is formed on at least one of the first layer structure and the second layer structure. The first layer structure is formed between the first substrate and the second layer structure.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: September 22, 2020
    Assignee: MEDIATEK INC.
    Inventors: Wen-Sung Hsu, Tao Cheng, Nan-Cheng Chen, Che-Ya Chou, Wen-Chou Wu, Yen-Ju Lu, Chih-Ming Hung, Wei-Hsiu Hsu
  • Patent number: 10680727
    Abstract: An over-the-air (OTA) wireless test system includes a container, a machine plate disposed on the container, a supporter disposed on the machine plate, a load board disposed on the supporter, a socket disposed on the load board, a device under test (DUT) installed in the socket, and a wave-guiding feature in the socket and the load board configured to pass and guide electromagnetic waves to and/or from an antenna structure of the DUT. The wave-guiding feature comprises a wave-guiding channel in the socket defined by a plurality of pogo pins surrounding the antenna structure of the DUT. The wave-guiding feature may further comprise a radiation passage in the load board defined by rows of via fence extending through an entire thickness of the load board.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: June 9, 2020
    Assignee: MediaTek Inc.
    Inventors: Yen-Ju Lu, Chih-Ming Hung, Wen-Chou Wu, Nan-Cheng Chen
  • Patent number: 10515887
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first carrier substrate having a first surface and an opposing second surface. A second carrier substrate is stacked on the first carrier substrate and has a first surface and an opposing second surface that faces the first surface of the first carrier substrate. A semiconductor die is mounted on the first surface of the second carrier substrate. A heat spreader is disposed on the first surface of the first carrier substrate to cover and surround the second carrier substrate and the semiconductor die. A method for forming the semiconductor package structure is also provided.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: December 24, 2019
    Assignee: MediaTek Inc.
    Inventors: Shih-Yi Syu, Chia-Yu Jin, Che-Ya Chou, Wen-Sung Hsu, Nan-Cheng Chen
  • Publication number: 20190355697
    Abstract: An electronic package configured to operate at Gigabit-per-second (Gbps) data rates is disclosed. The electronic package includes a package substrate of a rectangular shape. A chip package having a first high-speed interface circuit die is mounted on a top surface of the package substrate. The chip package is rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through about 45 degrees. The first high-speed interface circuit die includes a first Serializer/Deserializer (SerDes) circuit block.
    Type: Application
    Filed: April 29, 2019
    Publication date: November 21, 2019
    Inventors: Min-Chen Lin, Yi-Hui Lee, Che-Ya Chou, Nan-Cheng Chen
  • Publication number: 20190115646
    Abstract: A semiconductor package includes a substrate having thereon at least an antenna layer and a ground reflector layer under the antenna layer, a radio frequency (RF) die disposed on or in the substrate, an encapsulation layer disposed on the antenna layer of the substrate, and a frequency-selective surface (FSS) structure disposed on the encapsulation layer. The FSS structure is a two-dimensional periodic array of metal patterns of same shape and size. The FSS structure has highly reflective characteristic.
    Type: Application
    Filed: September 3, 2018
    Publication date: April 18, 2019
    Inventors: Shih-Chia Chiu, Yen-Ju Lu, Wen-Chou Wu, Nan-Cheng Chen
  • Publication number: 20190068300
    Abstract: An over-the-air (OTA) wireless test system includes a container, a machine plate disposed on the container, a supporter disposed on the machine plate, a load board disposed on the supporter, a socket disposed on the load board, a device under test (DUT) installed in the socket, and a wave-guiding feature in the socket and the load board configured to pass and guide electromagnetic waves to and/or from an antenna structure of the DUT. The wave-guiding feature comprises a wave-guiding channel in the socket defined by a plurality of pogo pins surrounding the antenna structure of the DUT. The wave-guiding feature may further comprise a radiation passage in the load board defined by rows of via fence extending through an entire thickness of the load board.
    Type: Application
    Filed: August 7, 2018
    Publication date: February 28, 2019
    Inventors: Yen-Ju Lu, Chih-Ming Hung, Wen-Chou Wu, Nan-Cheng Chen
  • Publication number: 20190051609
    Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure and a first antenna layer. The first antenna layer is formed on at least one of the first layer structure and the second layer structure. The first layer structure is formed between the first substrate and the second layer structure.
    Type: Application
    Filed: October 18, 2018
    Publication date: February 14, 2019
    Inventors: Wen-Sung HSU, Tao CHENG, Nan-Cheng CHEN, Che-Ya CHOU, Wen-Chou WU, Yen-Ju LU, Chih-Ming HUNG, Wei-Hsiu HSU
  • Publication number: 20180358685
    Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.
    Type: Application
    Filed: May 9, 2018
    Publication date: December 13, 2018
    Inventors: Fu-Yi Han, Che-Ya Chou, Che-Hung Kuo, Wen-Chou Wu, Nan-Cheng Chen
  • Patent number: 10128192
    Abstract: A semiconductor package structure including a redistribution layer (RDL) structure having a first surface and a second surface opposite thereto is provided. The RDL structure includes an inter-metal dielectric (IMD) layer and a first conductive layer disposed at a first layer-level of the IMD layer. A molding compound covers the first surface of the RDL structure. A first semiconductor die is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. A plurality of bump structures is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: November 13, 2018
    Assignee: MEDIATEK INC.
    Inventors: Min-Chen Lin, Che-Ya Chou, Nan-Cheng Chen
  • Patent number: 10103128
    Abstract: A semiconductor package is provided. The semiconductor package includes a carrier substrate having opposite first surface and second surface, and a chip stack disposed on the first surface of the carrier substrate. The chip stack includes a first semiconductor die, a second semiconductor die, and an interposer between the first semiconductor die and the second semiconductor die. The interposer transmits signals between the first semiconductor die and the second semiconductor die.
    Type: Grant
    Filed: May 7, 2017
    Date of Patent: October 16, 2018
    Assignee: MEDIATEK INC.
    Inventors: Che-Ya Chou, Kun-Ting Hung, Chia-Hao Yang, Nan-Cheng Chen
  • Publication number: 20180102298
    Abstract: A semiconductor device includes a substrate, a body structure and an electronic component. The body structure is disposed above the substrate and includes a semiconductor die, a molding compound, a conductive component and a lower redistribution layer (RDL). The semiconductor die has an active surface. The molding compound encapsulates the semiconductor die and has a lower surface, an upper surface opposite to the lower surface and a through hole extending to the upper surface from the lower surface. The conductive component is formed within the through hole. The lower RDL is formed on the lower surface of the molding compound, the active surface of the semiconductor die and the conductive component exposed from the lower surface. The electronic component is disposed above the upper surface of the molding compound and electrically connected to the lower RDL through the conductive component.
    Type: Application
    Filed: October 2, 2017
    Publication date: April 12, 2018
    Inventors: Nan-Cheng Chen, Che-Ya Chou, Hsing-Chih Liu, Che-Hung Kuo
  • Publication number: 20180082936
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first carrier substrate having a first surface and an opposing second surface. A second carrier substrate is stacked on the first carrier substrate and has a first surface and an opposing second surface that faces the first surface of the first carrier substrate. A semiconductor die is mounted on the first surface of the second carrier substrate. A heat spreader is disposed on the first surface of the first carrier substrate to cover and surround the second carrier substrate and the semiconductor die. A method for forming the semiconductor package structure is also provided.
    Type: Application
    Filed: September 11, 2017
    Publication date: March 22, 2018
    Inventors: Shih-Yi SYU, Chia-Yu JIN, Che-Ya CHOU, Wen-Sung HSU, Nan-Cheng CHEN
  • Publication number: 20180053665
    Abstract: A pre-bumped redistribution layer (RDL) structure is disclosed. The pre-bumped RDL structure includes at least a dielectric layer, a first metal layer on the first surface, a second metal layer on the second surface, and a via layer electrically connecting the first metal layer and the second metal layer. At least a bump pad is formed in the first metal layer. A bump is disposed on the bump pad. The bump comprises a copper layer with its lower end directly jointed to a top surface of the bump pad.
    Type: Application
    Filed: June 14, 2017
    Publication date: February 22, 2018
    Inventors: Che-Hung Kuo, Che-Ya Chou, Nan-Cheng Chen
  • Publication number: 20180025985
    Abstract: A semiconductor package structure including a redistribution layer (RDL) structure having a first surface and a second surface opposite thereto is provided. The RDL structure includes an inter-metal dielectric (IMD) layer and a first conductive layer disposed at a first layer-level of the IMD layer. A molding compound covers the first surface of the RDL structure. A first semiconductor die is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. A plurality of bump structures is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure.
    Type: Application
    Filed: April 27, 2017
    Publication date: January 25, 2018
    Inventors: Min-Chen LIN, Che-Ya CHOU, Nan-Cheng CHEN