Patents by Inventor Nan-Cheng Chen
Nan-Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11908759Abstract: A semiconductor device includes a substrate, a body structure and an electronic component. The body structure is disposed above the substrate and includes a semiconductor die, a molding compound, a conductive component and a lower redistribution layer (RDL). The semiconductor die has an active surface. The molding compound encapsulates the semiconductor die and has a lower surface, an upper surface opposite to the lower surface and a through hole extending to the upper surface from the lower surface. The conductive component is formed within the through hole. The lower RDL is formed on the lower surface of the molding compound, the active surface of the semiconductor die and the conductive component exposed from the lower surface. The electronic component is disposed above the upper surface of the molding compound and electrically connected to the lower RDL through the conductive component.Type: GrantFiled: March 3, 2021Date of Patent: February 20, 2024Assignee: MediaTek Inc.Inventors: Nan-Cheng Chen, Che-Ya Chou, Hsing-Chih Liu, Che-Hung Kuo
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Patent number: 11848481Abstract: A semiconductor package includes a substrate having thereon at least an antenna layer and a ground reflector layer under the antenna layer, a radio frequency (RF) die disposed on or in the substrate, a molding compound disposed on the antenna layer of the substrate, and a frequency-selective surface (FSS) structure disposed on the molding compound. The FSS structure is a two-dimensional periodic array of metal patterns of same shape and size. The FSS structure has highly reflective characteristic.Type: GrantFiled: April 4, 2022Date of Patent: December 19, 2023Assignee: MediaTek Inc.Inventors: Shih-Chia Chiu, Yen-Ju Lu, Wen-Chou Wu, Nan-Cheng Chen
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Patent number: 11837552Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.Type: GrantFiled: May 19, 2022Date of Patent: December 5, 2023Assignee: MediaTek Inc.Inventors: Wen-Sung Hsu, Tao Cheng, Nan-Cheng Chen, Che-Ya Chou, Wen-Chou Wu, Yen-Ju Lu, Chih-Ming Hung, Wei-Hsiu Hsu
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Patent number: 11721882Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.Type: GrantFiled: October 20, 2020Date of Patent: August 8, 2023Assignee: MediaTek Inc.Inventors: Fu-Yi Han, Che-Ya Chou, Che-Hung Kuo, Wen-Chou Wu, Nan-Cheng Chen, Min-Chen Lin, Hsing-Chih Liu
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Publication number: 20220352084Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.Type: ApplicationFiled: May 19, 2022Publication date: November 3, 2022Applicant: MediaTek Inc.Inventors: Wen-Sung Hsu, Tao Cheng, Nan-Cheng Chen, Che-Ya Chou, Wen-Chou Wu, Yen-Ju Lu, Chih-Ming Hung, Wei-Hsiu Hsu
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Publication number: 20220302574Abstract: A semiconductor package includes a substrate having thereon at least an antenna layer and a ground reflector layer under the antenna layer, a radio frequency (RF) die disposed on or in the substrate, a molding compound disposed on the antenna layer of the substrate, and a frequency-selective surface (FSS) structure disposed on the molding compound. The FSS structure is a two-dimensional periodic array of metal patterns of same shape and size. The FSS structure has highly reflective characteristic.Type: ApplicationFiled: April 4, 2022Publication date: September 22, 2022Applicant: MediaTek Inc.Inventors: Shih-Chia Chiu, Yen-Ju Lu, Wen-Chou Wu, Nan-Cheng Chen
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Patent number: 11373957Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.Type: GrantFiled: August 17, 2020Date of Patent: June 28, 2022Assignee: MediaTek Inc.Inventors: Wen-Sung Hsu, Tao Cheng, Nan-Cheng Chen, Che-Ya Chou, Wen-Chou Wu, Yen-Ju Lu, Chih-Ming Hung, Wei-Hsiu Hsu
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Patent number: 11322823Abstract: A semiconductor package includes a substrate having thereon at least an antenna layer and a ground reflector layer under the antenna layer, a radio frequency (RF) die disposed on or in the substrate, an encapsulation layer disposed on the antenna layer of the substrate, and a frequency-selective surface (FSS) structure disposed on the encapsulation layer. The FSS structure is a two-dimensional periodic array of metal patterns of same shape and size. The FSS structure has highly reflective characteristic.Type: GrantFiled: September 3, 2018Date of Patent: May 3, 2022Assignee: MediaTek Inc.Inventors: Shih-Chia Chiu, Yen-Ju Lu, Wen-Chou Wu, Nan-Cheng Chen
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Publication number: 20210202425Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor device bonded to a base through a first conductive structure. The semiconductor device includes a carrier substrate including a conductive trace. A portion of the conductive trace is elongated. The semiconductor device also includes a second conductive structure above the carrier substrate. A portion of the second conductive structure is in contact with the portion of the conductive trace. The semiconductor device further includes a semiconductor body mounted above the conductive trace. The semiconductor body is connected to the second conductive structure.Type: ApplicationFiled: March 11, 2021Publication date: July 1, 2021Applicant: MediaTek Inc.Inventors: Che-Ya Chou, Wen-Sung Hsu, Nan-Cheng Chen
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Publication number: 20210193540Abstract: A semiconductor device includes a substrate, a body structure and an electronic component. The body structure is disposed above the substrate and includes a semiconductor die, a molding compound, a conductive component and a lower redistribution layer (RDL). The semiconductor die has an active surface. The molding compound encapsulates the semiconductor die and has a lower surface, an upper surface opposite to the lower surface and a through hole extending to the upper surface from the lower surface. The conductive component is formed within the through hole. The lower RDL is formed on the lower surface of the molding compound, the active surface of the semiconductor die and the conductive component exposed from the lower surface. The electronic component is disposed above the upper surface of the molding compound and electrically connected to the lower RDL through the conductive component.Type: ApplicationFiled: March 3, 2021Publication date: June 24, 2021Applicant: MediaTek Inc.Inventors: Nan-Cheng Chen, Che-Ya Chou, Hsing-Chih Liu, Che-Hung Kuo
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Patent number: 10991669Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor device bonded to a base through a first conductive structure. The semiconductor device includes a carrier substrate including a conductive trace. A portion of the conductive trace is elongated. The semiconductor device also includes a second conductive structure above the carrier substrate. A portion of the second conductive structure is in contact with the portion of the conductive trace. The semiconductor device further includes a semiconductor body mounted above the conductive trace. The semiconductor body is connected to the second conductive structure.Type: GrantFiled: August 16, 2016Date of Patent: April 27, 2021Assignee: MediaTek Inc.Inventors: Che-Ya Chou, Wen-Sung Hsu, Nan-Cheng Chen
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Publication number: 20210036405Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.Type: ApplicationFiled: October 20, 2020Publication date: February 4, 2021Applicant: MediaTek Inc.Inventors: Fu-Yi Han, Che-Ya Chou, Che-Hung Kuo, Wen-Chou Wu, Nan-Cheng Chen, Min-Chen Lin, Hsing-Chih Liu
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Publication number: 20200381365Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.Type: ApplicationFiled: August 17, 2020Publication date: December 3, 2020Inventors: Wen-Sung HSU, Tao CHENG, Nan-Cheng CHEN, Che-Ya CHOU, Wen-Chou WU, Yen-Ju LU, Chih-Ming HUNG, Wei-Hsiu HSU
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Patent number: 10847869Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.Type: GrantFiled: May 9, 2018Date of Patent: November 24, 2020Assignee: MediaTek Inc.Inventors: Fu-Yi Han, Che-Ya Chou, Che-Hung Kuo, Wen-Chou Wu, Nan-Cheng Chen, Min-Chen Lin, Hsing-Chih Liu
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Patent number: 10784206Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure and a first antenna layer. The first antenna layer is formed on at least one of the first layer structure and the second layer structure. The first layer structure is formed between the first substrate and the second layer structure.Type: GrantFiled: October 18, 2018Date of Patent: September 22, 2020Assignee: MEDIATEK INC.Inventors: Wen-Sung Hsu, Tao Cheng, Nan-Cheng Chen, Che-Ya Chou, Wen-Chou Wu, Yen-Ju Lu, Chih-Ming Hung, Wei-Hsiu Hsu
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Patent number: 10680727Abstract: An over-the-air (OTA) wireless test system includes a container, a machine plate disposed on the container, a supporter disposed on the machine plate, a load board disposed on the supporter, a socket disposed on the load board, a device under test (DUT) installed in the socket, and a wave-guiding feature in the socket and the load board configured to pass and guide electromagnetic waves to and/or from an antenna structure of the DUT. The wave-guiding feature comprises a wave-guiding channel in the socket defined by a plurality of pogo pins surrounding the antenna structure of the DUT. The wave-guiding feature may further comprise a radiation passage in the load board defined by rows of via fence extending through an entire thickness of the load board.Type: GrantFiled: August 7, 2018Date of Patent: June 9, 2020Assignee: MediaTek Inc.Inventors: Yen-Ju Lu, Chih-Ming Hung, Wen-Chou Wu, Nan-Cheng Chen
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Patent number: 10515887Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first carrier substrate having a first surface and an opposing second surface. A second carrier substrate is stacked on the first carrier substrate and has a first surface and an opposing second surface that faces the first surface of the first carrier substrate. A semiconductor die is mounted on the first surface of the second carrier substrate. A heat spreader is disposed on the first surface of the first carrier substrate to cover and surround the second carrier substrate and the semiconductor die. A method for forming the semiconductor package structure is also provided.Type: GrantFiled: September 11, 2017Date of Patent: December 24, 2019Assignee: MediaTek Inc.Inventors: Shih-Yi Syu, Chia-Yu Jin, Che-Ya Chou, Wen-Sung Hsu, Nan-Cheng Chen
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Publication number: 20190355697Abstract: An electronic package configured to operate at Gigabit-per-second (Gbps) data rates is disclosed. The electronic package includes a package substrate of a rectangular shape. A chip package having a first high-speed interface circuit die is mounted on a top surface of the package substrate. The chip package is rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through about 45 degrees. The first high-speed interface circuit die includes a first Serializer/Deserializer (SerDes) circuit block.Type: ApplicationFiled: April 29, 2019Publication date: November 21, 2019Inventors: Min-Chen Lin, Yi-Hui Lee, Che-Ya Chou, Nan-Cheng Chen
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Publication number: 20190115646Abstract: A semiconductor package includes a substrate having thereon at least an antenna layer and a ground reflector layer under the antenna layer, a radio frequency (RF) die disposed on or in the substrate, an encapsulation layer disposed on the antenna layer of the substrate, and a frequency-selective surface (FSS) structure disposed on the encapsulation layer. The FSS structure is a two-dimensional periodic array of metal patterns of same shape and size. The FSS structure has highly reflective characteristic.Type: ApplicationFiled: September 3, 2018Publication date: April 18, 2019Inventors: Shih-Chia Chiu, Yen-Ju Lu, Wen-Chou Wu, Nan-Cheng Chen
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Publication number: 20190068300Abstract: An over-the-air (OTA) wireless test system includes a container, a machine plate disposed on the container, a supporter disposed on the machine plate, a load board disposed on the supporter, a socket disposed on the load board, a device under test (DUT) installed in the socket, and a wave-guiding feature in the socket and the load board configured to pass and guide electromagnetic waves to and/or from an antenna structure of the DUT. The wave-guiding feature comprises a wave-guiding channel in the socket defined by a plurality of pogo pins surrounding the antenna structure of the DUT. The wave-guiding feature may further comprise a radiation passage in the load board defined by rows of via fence extending through an entire thickness of the load board.Type: ApplicationFiled: August 7, 2018Publication date: February 28, 2019Inventors: Yen-Ju Lu, Chih-Ming Hung, Wen-Chou Wu, Nan-Cheng Chen