Abstract: Disclosed is a method for designing a semiconductor device. In an existing semiconductor design, a time delay effect caused by a dummy metal interconnection cannot be reflected. In order to address this disadvantage, a real metal fill pattern and a virtual metal fill pattern are employed for a layout parasitic extract step such that a time delay effect caused by the dummy metal pattern in semiconductor design is reflected. Accordingly, a semiconductor device can be designed by effectively reflecting a time delay effect. According to the method, since a real metal fill pattern and a virtual metal fill pattern are employed for a layout parasitic extract step so that resistor capacitance values of interconnections (including dummy interconnections) between logic elements are extracted, it is possible to more exactly design a semiconductor device by tacking a time delay effect into account.