Abstract: The present invention relates to a process for thinning a semiconductor wafer. Two surfaces of the wafer separately form a surface-bond glue (layer) and a surface protective glue (layer). The thinning process is applied to the wafer before forming the surface protective glue. Once the baking and drying process is applied to the surface-bond glue and the surface protective glue it then cuts the wafer. Finally, it dissolves the lower solubility of the surface protective glue to obtain the finished goods. The necessity of the selection of the wafer may serve to maintain quality standards. The wafer thinning process of the present invention is suitable for the extremely thin wafer. Thus, it reduces the production cost.

Abstract: The present invention relates to a process for thinning a semiconductor wafer. Two surfaces of the wafer separately form a surface-bond glue (layer) and a surface protective glue (layer). The thinning process is applied to the wafer before forming the surface protective glue. Once the baking and drying process is applied to the surface-bond glue and the surface protective glue it then cuts the wafer. Finally, it dissolves the lower solubility of the surface protective glue to obtain the finished goods. The necessity of the selection of the wafer may serve to maintain quality standards. The wafer thinning process of the present invention is suitable for the extremely thin wafer. Thus, it reduces the production cost.

Abstract: A trench capacitor and the method of manufacturing the same are provided. A rough polysilicon layer is formed on an inner electrode layer and subsequently mantled by a dielectric layer, and then filled up with an outer electrode layer. The present invention utilizes the characteristic that the rough polysilicon layer has bigger surface area to substantially increase the contact area between the dielectric layer and the inner electrode layer, and make the capacitance of the capacitor increase.

Abstract: An ion doping method to form source and drain is disclosed. First form a gate structure and a gate spacer on a semiconductor substrate, and then use dielectric layer having trenches therein to define heavily ion-doped positions and use a Y-shaped polysilicon layer formed in the trenches. Perform an ion implantation, by using the polysilicon layer, gate spacer and dielectric layer as a barrier layer, to naturally form ion doped regions of source/drain, so as to make components, which are minimized in the increased packing density, still have a gate structure keeping an enough channel length.

Abstract: A dynamic random access memory (DRAM) integrated circuit (10). The DRAM (10) includes a recessed region (20) defined in a semiconductor substrate (22). This recessed region has substantially vertical sides (34) extending from a bottom surface (32). A field effect transistor (18) is defined adjacent to the recessed region (20). A capacitor structure, including a lower capacitor plate (26), a capacitor dielectric (28), and an upper capacitor plate (30), is defined in the recessed region (20) and over the field effect transistor (18), thereby providing a greater capacitor surface.

Abstract: A dynamic random access memory (DRAM) integrated circuit (10). The DRAM (10) includes a recessed region (20) defined in a semiconductor substrate (22). This recessed region has substantially vertical sides (34) extending from a bottom surface (32). A field effect transistor (18) is defined adjacent to the recessed region (20). A capacitor structure, including a lower capacitor plate (26), a capacitor dielectric (28), and an upper capacitor plate (30), is defined in the recessed region (20) and over the field effect transistor (18), thereby providing a greater capacitor surface.

Abstract: A method and structure for a lower capacitor electrode for a dynamic random access integrated circuit. A polysilicon gate layer is formed over a thin layer of oxide in a first region of a semiconductor substrate. Another oxide layer is then formed overlying the polysilicon gate layer. A polysilicon layer which was doped by S/D implant including the lower capacitor electrode self-aligns and forms overlying a second region of the semiconductor substrate and over the oxide layer on the polysilicon gate layer. A nitride layer forms on the lower capacitor electrode portion overlying the second region. Exposed portions of the polysilicon layer are then oxidized. The S/D was formed by driving dopant from implanted second layer polysilicon. Portions of polysilicon under the nitride layer corresponding to the lower capacitor electrode oxidizes at a slower rate than the exposed portions of the polysilicon.

Abstract: A dynamic random access memory (DRAM) integrated circuit (10). The DRAM (10) includes a recessed region (20) defined in a semiconductor substrate (22). This recessed region has substantially vertical sides (34) extending from a bottom surface (32). A field effect transistor (18) is defined adjacent to the recessed region (20). A capacitor structure, including a lower capacitor plate (26), a capacitor dielectric (28), and an upper capacitor plate (30), is defined in the recessed region (20) and over the field effect transistor (18), thereby providing a greater capacitor surface.

Abstract: A method and structure for a lower capacitor electrode for a dynamic random access integrated circuit. A polysilicon gate layer is formed over a thin layer of oxide in a first region of a semiconductor substrate. Another oxide layer is then formed overlying the polysilicon gate layer. A polysilicon layer which was doped by S/D implant including the lower capacitor electrode self-aligns and forms overlying a second region of the semiconductor substrate and over the oxide layer on the polysilicon gate layer. A nitride layer forms on the lower capacitor electrode portion overlying the second region. Exposed portions of the polysilicon layer are then oxidized. The S/D was formed by driving dopant from implanted second layer polysilicon. Portions of polysilicon under the nitride layer corresponding to the lower capacitor electrode oxidizes at a slower rate than the exposed portions of the polysilicon.

Abstract: A resistor located above the semiconductive substrate of an integrated circuit chip can be made smaller than prior art resistors because no area is allocated for resistor contacts. During manufacture, a resistive strip having the width of the intended resistor is formed. A photoresist mask protects the top and sides of the resistive strip where the resistor is located, and etching exposes the ends but not the top and sides of the resistor. Contact to the resistor occurs at the upwardly extending (usually near vertical) end surfaces of the resistor.

Abstract: A process of forming a self-aligned oxide layer covering conductive structures such as MOS transistor gates above a semiconductive substrate while portions of the substrate such as source/drain regions are exposed involves forming side wall spacers against the gates, applying refractory metal to the exposed surface, heating the refractory metal so that it forms refractory silicide at regions where the refractory metal contacts the substrate, removing the unreacted refractory metal, and oxidizing the exposed refractory silicide with a low temperature wet oxidation which causes faster oxide growth above the highly doped gates than above the lightly doped source/drain regions. Subsequent etching of the differentially grown oxide layer exposes the source/drain regions while leaving protected the gate regions. Since no mask was needed for forming and patterning the gate-covering oxide, no misalignment can occur and thus no space need be allowed in the circuit layout for misalignment.

Abstract: A resistor located above the semiconductive substrate of an integrated circuit chip can be made smaller than prior art resistors because no area is allocated for resistor contacts. During manufacture, a resistive strip having the width of the intended resistor is formed. A photoresist mask protects the top and sides of the resistive strip where the resistor is located, and etching exposes the ends but not the top and sides of the resistor. Contact to the resistor occurs at the upwardly extending (usually near vertical) end surfaces of the resistor.

Abstract: A method for forming substrate contacts in an integrated circuit structure uses a layer of conductive material, preferably polycrystalline silicon, applied to the surface of the semiconductor structure to make electrical contact with exposed portions of the substrate. The polycrystalline silicon layer is then coated with a nitride layer. A via mask which is opaque over the region where a contact will be formed produces a photoresist stud smaller that the original via mask. The photoresist stud is used to pattern the nitride to remain only over the contact region. Following this, the polycrystalline silicon is oxidized except at the nitride mask, forming a bird's beak beneath edges of the nitride. The resulting contact is smaller than the photolithographic limit of the via mask and thus allows for smaller space allocated for contact regions and smaller total structure.

Abstract: A process for forming a resistor structure which comprises a polysilicon strip having a resistor region with tungsten leads formed on opposite ends of the strip. A protective oxide is grown on the sides of the silicon strip preventing undercutting of the oxide layer disposed beneath this strip. This prevents formation of the tungsten under the strip or along the sides of the strip which would otherwise place stress on the strip in addition causing other problems.