Patents by Inventor Nan Kawashima

Nan Kawashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100176874
    Abstract: Provided is a voltage detection circuit having a small circuit scale. A P-type metal oxide semiconductor (PMOS) transistor (11) has an absolute value (Vtp) of its threshold voltage, which is equal to a minimum operating voltage. If a power supply voltage (VDD) becomes higher than the minimum operating voltage, the PMOS transistor (11) is turned ON to allow a current to flow therethrough. As a result, based on the current, an output voltage (Vout) is generated across a capacitor (15).
    Type: Application
    Filed: January 13, 2010
    Publication date: July 15, 2010
    Inventors: Masakazu Sugiura, Atsushi Igarashi, Nan Kawashima
  • Patent number: 7750722
    Abstract: A charge pump circuit has an input voltage generating circuit and a voltage step-up circuit. The input voltage generating circuit has a constant current circuit that generates a constant current, a charge transfer correction device that generates a correction voltage based on the constant current, a constant voltage circuit that generates a constant voltage, and a buffer amplifier that outputs an input voltage obtained by adding the correction voltage to the constant voltage. The voltage step-up circuit has charge transfer devices, capacitors and a clock driver. The charge transfer devices are connected in series to an output terminal of the buffer amplifier and are made of the same element as and have substantially the same characteristic as that of the charge transfer correction device. Each of the capacitors has one end connected to each connection point of each of the plurality of charge transfer devices.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: July 6, 2010
    Assignee: Seiko Instruments Inc.
    Inventor: Nan Kawashima
  • Publication number: 20090184753
    Abstract: Provided is a charge pump circuit capable of shortening a settling time. When a boosted voltage (Vout) becomes high to be equal to or larger than an overshoot voltage, a transistor (T1) is turned on and an output terminal of the charge pump circuit is discharged. Accordingly, it is easy to reduce the boosted voltage (Vout) after an occurrence of an overshoot, and a period of time in which the boosted voltage (Vout) decreases from a voltage after the occurrence of the overshoot to a desired voltage is shortened, leading to a reduction in a settling time.
    Type: Application
    Filed: January 15, 2009
    Publication date: July 23, 2009
    Inventors: Nan Kawashima, Fumiyasu Utsunomiya
  • Publication number: 20080303585
    Abstract: A charge pump circuit is provided for stably obtaining a stepped-up voltage even if a temperature varies. The charge pump circuit has a structure in which a voltage corresponding to a voltage which is dropped by a charge transfer device is generated by a charge transfer device for correction, and the generated voltage is applied to an input voltage of the charge pump circuit. In addition, a voltage amplitude of a clock pulse for a step-up operation is adapted to be an amplitude based on the input voltage.
    Type: Application
    Filed: June 4, 2008
    Publication date: December 11, 2008
    Inventor: Nan Kawashima