Abstract: A phase locked loop (PLL), including a phase-frequency detector receiving two clock signals and outputting a phase detection signal corresponding to the phase difference between the two clock signals is provided. A controller receives the phase detection signal and generates a first control signal and a second control signal according to the phase detection signal, an oscillator receiving the first control signal and outputting a first output clock signal with a folded period corresponding to the first control signal and a loop divider receiving the second control signal and the first output clock signal dividing the frequency of the first output clock signal by an integer unfolding divisor corresponding to the second control signal and outputting a second output clock signal coupled to the phase-frequency detector. The PLL eliminates unlocked frequencies for all process imperfections, has decreased circuit area and provides a broad output bandwidth.

Abstract: The invention relates to an Overlap and Add circuit, and in particular, an adaptive Overlap and Add circuit. The adaptive OLA circuit comprises a detection unit, an estimator, and an OLA circuit. The detection unit estimates a channel property according to an OFDM signal received through a channel. The estimator estimates an OLA length in a current OFDM symbol of an OFDM signal according to a channel property. The OLA circuit copies an OLA signal to an FFT window in the current symbol according to the OLA length.

Abstract: A method for obtaining sampling frequency offset of an Orthogonal Frequency Division Multiplexed symbol in an OFDM receiver. The method comprises obtaining a first series of pilot pairs, wherein each pilot pair is symmetric with a dc point of a frequency axis, and each pilot pair has a first pilot value, obtaining a first difference of each pilot, obtaining a first group difference, wherein the first group difference is a summation of the first differences of the first series, and obtaining SFO information by obtaining difference between real and image parts of the first group difference.

Abstract: An automatically adjusting gain/bandwidth loop filter suitable for a digital phase lock loop or a digital adaptive carrier recovery loop with variable loop gain/bandwidth for rapid acquisition and lower steady-state jitter is provided. The automatically adjusting gain/bandwidth loop filter comprises a variable gain/bandwidth loop filter, a tracking status detector and a gain/bandwidth control state machine. The tracking status detector observes the frequency error which is the output of the frequency tracking (integral) branch of the variable gain/bandwidth loop filter, then it outputs a tracking state of the carrier recovery loop. The loop gain/bandwidth is then adjusted by the gain/bandwidth control state machine in response of the tracking state to improve the pull-in time and steady-state carrier frequency jitter.