Patents by Inventor Nan Mou
Nan Mou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240123070Abstract: The present invention provides an epitope peptide of a RAS G13D mutant, an antigen presenting cell expressing the epitope peptide, a tumor vaccine containing the antigen presenting cell, and a use of the tumor vaccine in the prevention or treatment of a tumor having RAS G13D mutation. The present invention also provides a T cell receptor (TCR) specifically recognizing a RAS G13D mutant, a conjugate and a fusion protein containing the TCR, an immune cell expressing the TCR, a T cell drug containing the immune cell, and a use of the T cell drug in the prevention or treatment of a tumor having RAS G13D mutation.Type: ApplicationFiled: January 29, 2022Publication date: April 18, 2024Inventors: Nan Mou, Yue Yu, Jijun Yuan
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Publication number: 20240071535Abstract: Provided is an anti-fuse memory including a anti-fuse memory cell including an isolation structure, a select gate, first and second gate insulating layers, an anti-fuse gate, and first, second and third doped regions. The isolation structure is disposed in a substrate. The select gate is disposed on the substrate. The first gate insulating layer is disposed between the select gate and the substrate. The anti-fuse gate is disposed on the substrate and partially overlapped with the isolation structure. The second gate insulating layer is disposed between the anti-fuse gate and the substrate. The first doped region and the second doped region are disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate. The third doped region is disposed in the substrate and located between the first doped region and the isolation structure.Type: ApplicationFiled: October 16, 2022Publication date: February 29, 2024Applicant: United Microelectronics Corp.Inventors: Chung-Hao Chen, Chi-Hsiu Hsu, Chi-Fa Lien, Ying-Ting Lin, Cheng-Hsiao Lai, Ya-Nan Mou
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Publication number: 20240000834Abstract: The present invention relates to the field of immunology and tumor treatment. Specifically, an Ras G12V mutant epitope peptide, an antigen presenting cell expressing the epitope peptide, a tumor vaccine containing same, and a use of the tumor vaccine in preventing or treating a tumor having RAS G12V mutation. The present invention further relates to a T cell receptor (TCR) specifically recognizing an Ras G12V mutant, a conjugate and a fusion protein containing the TCR, an immune cell expressing the TCR, a T cell drug containing same, and a use of the T cell drug in preventing or treating a tumor having RAS G12V mutation.Type: ApplicationFiled: November 23, 2021Publication date: January 4, 2024Inventors: Nan Mou, Yue Yu, Jijun Yuan
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Publication number: 20230331862Abstract: The present application provides an antibody specifically bound to glycosylated CEACAM5, the preparation of a humanized antibody thereof and an application thereof.Type: ApplicationFiled: January 8, 2021Publication date: October 19, 2023Inventors: Nan Mou, Yue Yu, Jijun Yuan
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Publication number: 20220331363Abstract: An antibody specifically binding to BCMA and an antigen binding fragment thereof, a chimeric antigen receptor (CAR) containing the antigen binding fragment, a nucleic acid molecule encoding the CAR, an immune effect cell expressing the CAR, a method for preparing the immune effect cell, use of the CAR and the immune effect cell for preventing and/or treating a B cell-related disease (for example, a B-cell malignancy and an autoimmune disease), and a method for preventing and/or treating the B cell-related disease.Type: ApplicationFiled: September 20, 2019Publication date: October 20, 2022Inventors: Liang Du, Nan Mou, Hongyan Zhang, Lina Jin, Yue Yu, Jijun Yuan
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Patent number: 10777260Abstract: An SRAM cell includes two inverters and three transistors. The first inverter includes a first end coupled to a first storage node and a second end coupled to a second storage node. The second inverter includes a first end coupled to the second storage node and a second end coupled to the first storage node. The first transistor includes a first end coupled to the first storage node, a second end and a control end. The second transistor includes a first end coupled to the second end of the first transistor, a second end coupled to a first bit line, and a control end. The third transistor includes a first end coupled between the second end of the first transistor and the first end of the second transistor, a second end, and a control end coupled to the first storage node.Type: GrantFiled: October 16, 2019Date of Patent: September 15, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zih-Yu Chiu, Hsin-Wen Chen, Ya-Nan Mou, Yuan-Hui Chen, Chung-Cheng Tsai
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Patent number: 10580499Abstract: A read only memory (ROM) is provided in the present invention, which includes a plurality of bit lines extending in a first direction, a plurality of source lines extending in parallel to the plurality of bit lines, and a plurality of word lines extending in a second direction perpendicular to the first direction. Each two ROM cells share an active area and are electrically coupled to one of the plurality of source lines by a common source line contact.Type: GrantFiled: September 21, 2017Date of Patent: March 3, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hsin-Pang Lu, Chi-Hsiu Hsu, Chung-Hao Chen, Ya-Nan Mou, Chung-Cheng Tsai
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Publication number: 20190043587Abstract: A read only memory (ROM) is provided in the present invention, which includes a plurality of bit lines extending in a first direction, a plurality of source lines extending in parallel to the plurality of bit lines, and a plurality of word lines extending in a second direction perpendicular to the first direction. Each two ROM cells share an active area and are electrically coupled to one of the plurality of source lines by a common source line contact.Type: ApplicationFiled: September 21, 2017Publication date: February 7, 2019Inventors: Hsin-Pang Lu, Chi-Hsiu Hsu, Chung-Hao Chen, Ya-Nan Mou, Chung-Cheng Tsai
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Publication number: 20180292848Abstract: A voltage regulating circuit provides a feedback voltage and an output voltage based on a power voltage. The voltage regulating circuit includes a reference voltage generator and a compensating circuit. The reference voltage generator receives the power voltage, produces the feedback voltage, and includes an impedance having first and second terminals. The second terminal is coupled to a ground voltage and a first current flows through the impedance at the first terminal to produce the feedback voltage. The compensating circuit includes a negative threshold voltage (NVT) transistor having a source terminal, a drain terminal and a gate terminal. The source terminal receives a power voltage, the drain terminal is connected to the gate terminal and coupled to the first terminal of the impedance through a path to add a second current to the first current when the NVT transistor is turned on under an operational condition at the FF corner.Type: ApplicationFiled: May 26, 2017Publication date: October 11, 2018Applicant: United Microelectronics Corp.Inventors: Chai-Wei Fu, Cheng-Hsiao Lai, Ying-Ting Lin, Yuan-Hui Chen, Ya-Nan Mou, Yung-Hsiang Lin, Hsueh-Chen Cheng
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Patent number: 10095251Abstract: A voltage regulating circuit provides a feedback voltage and an output voltage based on a power voltage. The voltage regulating circuit includes a reference voltage generator and a compensating circuit. The reference voltage generator receives the power voltage, produces the feedback voltage, and includes an impedance having first and second terminals. The second terminal is coupled to a ground voltage and a first current flows through the impedance at the first terminal to produce the feedback voltage. The compensating circuit includes a negative threshold voltage (NVT) transistor having a source terminal, a drain terminal and a gate terminal. The source terminal receives a power voltage, the drain terminal is connected to the gate terminal and coupled to the first terminal of the impedance through a path to add a second current to the first current when the NVT transistor is turned on under an operational condition at the FF corner.Type: GrantFiled: May 26, 2017Date of Patent: October 9, 2018Assignee: United Microelectronics Corp.Inventors: Chai-Wei Fu, Cheng-Hsiao Lai, Ying-Ting Lin, Yuan-Hui Chen, Ya-Nan Mou, Yung-Hsiang Lin, Hsueh-Chen Cheng
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Patent number: 9571079Abstract: An integrated circuit includes a signal generating unit, a signal monitoring unit and a processing unit. The signal generating unit is configured to generate a control signal. The signal monitoring unit is configured to receive the control signal and accordingly output a monitor signal. The processing unit is configured to receive the monitor signal. The control signal is adjusted until the monitor signal is located within a preset range. A signal monitoring method used with the integrated circuit and a signal monitoring method used with a plurality of transistors are also provided.Type: GrantFiled: November 11, 2015Date of Patent: February 14, 2017Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Yu-Yee Liow, Ya-Nan Mou, Yuan-Hui Chen, Shih-Chin Lin, Po-Hua Chen, Wen-Hong Hsu
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Publication number: 20160373095Abstract: An integrated circuit includes a signal generating unit, a signal monitoring unit and a processing unit. The signal generating unit is configured to generate a control signal. The signal monitoring unit is configured to receive the control signal and accordingly output a monitor signal. The processing unit is configured to receive the monitor signal. The control signal is adjusted until the monitor signal is located within a preset range. A signal monitoring method used with the integrated circuit and a signal monitoring method used with a plurality of transistors are also provided.Type: ApplicationFiled: November 11, 2015Publication date: December 22, 2016Inventors: YU-YEE LIOW, YA-NAN MOU, YUAN-HUI CHEN, SHIH-CHIN LIN, PO-HUA CHEN, WEN-HONG HSU
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Patent number: 9263134Abstract: A non-volatile memory cell includes a plurality of rows of memory cells, a plurality of bit lines coupled to the plurality of rows of memory cells for accessing data to the plurality of rows of memory cells, a plurality of word lines each coupled to a corresponding row of memory cells, and a decoder coupled to the plurality of word lines for enabling at least one row of memory cells of the plurality of rows of memory cells.Type: GrantFiled: March 17, 2014Date of Patent: February 16, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ya-Nan Mou, Hsin-Pang Lu, Hsi-Wen Chen
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Patent number: 9160352Abstract: A phase-locked loop (PLL) and a method for controlling the PLL are provided. The PLL includes a phase detector, a charge pump, a voltage-controlled oscillator (VCO), a feedback frequency divider, and a detector circuit. The phase detector generates a direction signal according to a comparison between phases of a first clock signal and a second clock signal. The charge pump converts the direction signal into a control voltage. The VCO generates a third clock signal. The control voltage controls a frequency of the third clock signal. The feedback frequency divider divides the frequency of the third clock signal to generate the second clock signal. The detector circuit sends a pulse signal to restart the VCO when the control voltage conforms to a preset condition.Type: GrantFiled: May 27, 2014Date of Patent: October 13, 2015Assignee: United Microelectronics Corp.Inventors: Po-Hua Chen, Yu-Yee Liow, Wen-Hong Hsu, Hsueh-Chen Cheng, Ya-Nan Mou, Yuan-Hui Chen
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Publication number: 20150262621Abstract: A non-volatile memory cell includes a plurality of rows of memory cells, a plurality of bit lines coupled to the plurality of rows of memory cells for accessing data to the plurality of rows of memory cells, a plurality of word lines each coupled to a corresponding row of memory cells, and a decoder coupled to the plurality of word lines for enabling at least one row of memory cells of the plurality of rows of memory cells.Type: ApplicationFiled: March 17, 2014Publication date: September 17, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ya-Nan Mou, Hsin-Pang Lu, Hsi-Wen Chen
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Publication number: 20150095728Abstract: A testing method for non-volatile memory includes writing a first set of data to a set of addresses in a non-volatile memory, reading a second set of data from the set of addresses, and writing the first set of data to the set of addresses again if the first set of data and the second set of data are not identical and number of times for writing the first set of data to the set of addresses is smaller than a predetermined number.Type: ApplicationFiled: September 30, 2013Publication date: April 2, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hsin-Pang Lu, Hsi-Wen Chen, Ya-Nan Mou, Chung-Cheng Tsai, Hsiao-Chieh Sung, Yin-Ju Hsiao
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Patent number: 8873295Abstract: An operation method of a memory includes the following steps: determining the number of memory units required to update the content stored therein when the memory is performing a program operation based on the N-bit input data and accordingly generate a first determination result; and providing (N?M) number of loads to a source line decoder of the memory if the first determination result indicates that there are M number of memory units required to update the content stored therein, and thereby coupling the (N?M) number of the provided loads to a transmission path of a power supply voltage in parallel, wherein N and M are natural numbers. A memory is also provided.Type: GrantFiled: November 27, 2012Date of Patent: October 28, 2014Assignee: United Microelectronics CorporationInventors: Shi-Wen Chen, Chi-Chang Shuai, Chung-Cheng Tsai, Ya-Nan Mou
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Patent number: 8804440Abstract: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.Type: GrantFiled: March 26, 2014Date of Patent: August 12, 2014Assignee: United Microelectronics CorporationInventors: Shi-Wen Chen, Hsin-Pang Lu, Chung-Cheng Tsai, Ya-Nan Mou
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Publication number: 20140211573Abstract: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.Type: ApplicationFiled: March 26, 2014Publication date: July 31, 2014Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Shi-Wen CHEN, Hsin-Pang LU, Chung-Cheng TSAI, Ya-Nan MOU
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Publication number: 20140204686Abstract: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of memory array processed by a program operation according to input data, and the comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust the value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.Type: ApplicationFiled: March 26, 2014Publication date: July 24, 2014Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Shi-Wen CHEN, Hsin-Pang Lu, Chung-Cheng Tsai, Ya-Nan Mou