Abstract: A signal control method suitable for a touch screen is provided. The signal control method comprises: switching a plurality of scan lines to an enabling voltage level sequentially in a display stage; turning on a plurality of switches sequentially to transmit a plurality of display data to a plurality of data lines when a first scan line of the plurality of scan lines is in an enabled voltage level, wherein a first switch of the plurality of switches is coupled to a first data line of the plurality of data lines, and the first data line corresponds to one of a plurality of dummy lines in a vertical direction, when the first scan line is in the enabled voltage level, the first switch is turned on after other switches are turned on; and setting the plurality of dummy lines to a touch voltage in a touch stage.

Abstract: A liquid crystal display and a test circuit thereof are provided. The test circuit has a plurality of signal pads, a first data distributor, a plurality of logic circuit units and N switches. N is a positive integer. The signal pads are configured to receive a test data signal, a voltage signal, an enable signal and a plurality of first switch control signals. The first data distributor distributes the test data signal to N output terminals of the first data distributor. Each of the logic circuit units generates a second switch control signal according to the voltage signal, the enable signal and a corresponding one of the first switch control signals. Each of the switches controls the electrical connection between an output terminal of the first data distributor coupled thereto and at least a data line coupled thereto.

Abstract: A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.

Abstract: A driving method for a display panel is provided. The display panel includes at least a first common signal line, at least a second common signal line and a plurality of pixels arranged as a pixel array. The pixel array includes a first pixel row and a second pixel row electrically connected to the first common signal line and the second common signal line, respectively. The driving method includes steps of: generating a first AC common signal; generating a second AC common signal, wherein the first AC common signal and the second AC common signal are inverse to each other; and providing the first and second AC common signal to the first and second pixel rows through the first and second common signal lines, respectively, by way of N-frame switch, wherein N is a positive integer.

Abstract: A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.

Abstract: A liquid crystal display and a test circuit thereof are provided. The test circuit has a plurality of signal pads, a first data distributor, a plurality of logic circuit units and N switches. N is a positive integer. The signal pads are configured to receive a test data signal, a voltage signal, an enable signal and a plurality of first switch control signals. The first data distributor distributes the test data signal to N output terminals of the first data distributor. Each of the logic circuit units generates a second switch control signal according to the voltage signal, the enable signal and a corresponding one of the first switch control signals. Each of the switches controls the electrical connection between an output terminal of the first data distributor coupled thereto and at least a data line coupled thereto.

Abstract: A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output to circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.

Abstract: A display panel includes scan lines, data lines and a multiplexer circuit. The data lines interlace with the scan lines. The multiplexer circuit includes switches, in which first terminals of the plurality of switches are electrically coupled to one terminals of the data lines, respectively, and the switches are configured to switch on in response to control signals. The data lines are configured to receive image data signals through the switches during enabling periods of the control signals, and at least two control signals of the control signals are synchronously asserted and have enabling periods that are partially overlapped. A method of transmitting signals in a display panel is also disclosed herein.

Abstract: An image display method of a half-source-driving (HSD) liquid crystal display (LCD) for mitigating the screen flickering effect caused by applying a frame rate control (FRC) algorithm in the LCD includes providing a first gate sequence corresponding to a pixel array in the LCD display. If a target gray level of the pixel array is an average value of a first gray level and a second gray level, write the first gray level to a plurality of sub-pixels of the pixel array being charged first according to the first gate sequence, and write the second gray level smaller than the first gray level to a plurality of sub-pixels of the pixel array being charged latter according to the first gate sequence.

Abstract: A driving method for a display panel is provided. The display panel includes at least a first common signal line, at least a second common signal line and a plurality of pixels arranged as a pixel array. The pixel array includes a first pixel row and a second pixel row electrically connected to the first common signal line and the second common signal line, respectively. The driving method includes steps of: generating a first AC common signal; generating a second AC common signal, wherein the first AC common signal and the second AC common signal are inverse to each other; and providing the first and second AC common signal to the first and second pixel rows through the first and second common signal lines, respectively, by way of N-frame switch, wherein N is a positive integer.

Abstract: In one aspect, an LCD includes a display panel with a pixel matrix having M scan lines and N data lines, and a multiplexer feed-through compensation circuit, which includes P signal lines for providing P video signals, P multiplexers, and K pairs of control lines providing K pairs of control signals. Each multiplexer is electrically coupled to a corresponding signal line and has K channels. Each channel includes first and second switches parallel-connected between the signal line and a corresponding data line for selectively transmitting the video signal to the corresponding data line. Each pair of control lines is respectively electrically coupled to the first and second switches of a corresponding channel of each multiplexer. Each pair of control signals are configured such that a time turning off one of the first and second switches is earlier than that turning off the other switch.

Abstract: An active liquid crystal display panel includes a pixel array, a gate driving circuit, a data driving circuit, and an analog buffer. The gate driving circuit is used for driving M first scan lines where M is a natural number. The analog buffer is coupled to the gate driving circuit and includes M buffer circuits and a regulator. Each buffer circuit drives a corresponding second scan line according to an output signal of a corresponding first scan line of the M first scan lines, and the regulator is used for maintaining at least one reference voltage supplied to the M buffer circuits.

Abstract: In one aspect, an LCD includes a display panel with a pixel matrix having M scan lines and N data lines, and a multiplexer feed-through compensation circuit, which includes P signal lines for providing P video signals, P multiplexers, and K pairs of control lines providing K pairs of control signals. Each multiplexer is electrically coupled to a corresponding signal line and has K channels. Each channel includes first and second switches parallel-connected between the signal line and a corresponding data line for selectively transmitting the video signal to the corresponding data line. Each pair of control lines is respectively electrically coupled to the first and second switches of a corresponding channel of each multiplexer. Each pair of control signals are configured such that a time turning off one of the first and second switches is earlier than that turning off the other switch.

Abstract: A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output to circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.

Abstract: A multiplexer circuit includes multiple groups of switches and multiple groups of control lines. Each control line in each one of the groups of control lines is coupled to a control end of at least one switch in corresponding one of the groups of switches, and each group of control lines is configured for synchronously transmitting an identical group of control signals. A display panel and method for transmitting signals in a display panel is also disclosed herein.

Abstract: An active liquid crystal display panel includes a pixel array, a gate driving circuit, a data driving circuit, and an analog buffer. The gate driving circuit is used for driving M first scan lines where M is a natural number. The analog buffer is coupled to the gate driving circuit and includes M buffer circuits and a regulator. Each buffer circuit drives a corresponding second scan line according to an output signal of a corresponding first scan line of the M first scan lines, and the regulator is used for maintaining at least one reference voltage supplied to the M buffer circuits.

Abstract: In one aspect of the invention, an analog buffer circuit includes a p-channel field effect transistor (PTFT) and an n-channel field effect transistor (NTFT). Each of the PTFT and NTFT has a source region and a drain region defining a channel region therebetween, formed on a substrate such that the drain regions of the PTFT and the NTFT are in substantial contact with each other, a gate layer formed over and insulated from the corresponding channel region, a source electrode insulated from the gate layer and electrically connected to the corresponding source region, and a common drain electrode insulated from the gate layer and the source electrode, and is electrically connected to the drain regions of both the PTFT and the NTFT through a via defined over the depletion region.

Abstract: A display apparatus includes a plurality of scan lines, a plurality of data lines, a plurality of pixel transistors, a plurality of pixel electrodes, a gate driver, a source driver and a discharge circuit. The data lines are intersected with the scan lines. Each of the pixel transistors is electrically coupled to a corresponding scan line and a corresponding data line, and each of the pixel electrodes is electrically coupled to a corresponding pixel transistor. The gate driver is electrically coupled to the scan lines, and the source driver is electrically coupled to the data lines. The discharge circuit is electrically coupled to the gate driver and the data lines. The discharge circuit starts when the display apparatus is turned off, to control the gate drive for turning on the pixel transistors simultaneously, and make the pixel electrodes be electrically communicated with a reference voltage.

Abstract: A detachable detection window suitable for being disposed on a sidewall of a plasma chamber is disclosed. The detachable detection window includes a base and a cannular tube. The base herein has a first linking-up part and a second linking-up part is formed at an end of the cannular tube. The base and the cannular tube are assembled to form the detachable detection window.

Abstract: A detachable detection window suitable for being disposed on a sidewall of a plasma chamber is disclosed. The detachable detection window includes a base and a cannular tube. The base herein has a first linking-up part and a second linking-up part is formed at an end of the cannular tube. The base and the cannular tube are assembled to form the detachable detection window.