Patents by Inventor Nan Zhuang

Nan Zhuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12001746
    Abstract: An electronic apparatus and a method for displaying an image on a display device are disclosed. The electronic apparatus includes a display device; an image acquisition device configured to acquire a surrounding image of the display device; and a processor configured to: determine a background image of the display device according to the surrounding image; acquire a target range and a target object in the background image; determine a target image according to the background image, the target range and the target object; and control the display device to display the target image, wherein the target image excludes the target object.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: June 4, 2024
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., PEKING UNIVERSITY
    Inventors: Shuai Wang, Yadong Mu, Jie Feng, Yiming Bai, Xiangye Wei, Qiong Wu, Ge Ou, Nan Zhuang, Guoqiang Gong
  • Publication number: 20230010947
    Abstract: Disclosed are an electronic apparatus, and a method for displaying an image on a display device. The electronic apparatus comprises: a display device; an image acquisition device, which is configured to acquire a surrounding image of the display device; and a processor, which is configured to determine a background image of the display device according to the surrounding image, acquire a target range, and a target object in the background image, determine a target image according to the background image, the target range and the target object, and control the display device to display the target image, wherein the target image does not include the target object.
    Type: Application
    Filed: May 25, 2021
    Publication date: January 12, 2023
    Inventors: Shuai WANG, Yadong MU, Jie FENG, Yiming Bai, Xiangye Wei, Qiong Wu, Ge OU, Nan ZHUANG, Guoqiang GONG
  • Patent number: 9171116
    Abstract: An apparatus and method are provided for removing redundant logic in a logic design of an integrated circuit (IC) design. The apparatus and method optimizes the integrated circuit by selecting stuck-at constant registers in the logic design, propagating a constant output value of the stuck-at constant registers across output nets of the stuck-at constant registers, identifying redundant logic in the logic design based on the propagation of the constant input value across the output net of the stuck-at constant register, and removing the redundant logic in the logic design.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: October 27, 2015
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Peng Zhang, Nan Zhuang, Yuhua Yang
  • Patent number: 7346862
    Abstract: One embodiment of the present invention provides a system that optimizes a logic network. During operation, the system receives a first logic network which defines a logical function, wherein the first logic network cannot be efficiently optimized by directly using an optimization process that preserves the logical function. Next, the system creates an intermediate logic network based on the first logic network, wherein the intermediate logic network defines an intermediate logical function which is different from the logical function, wherein the intermediate logic network can be efficiently optimized using the optimization process. The system then optimizes the intermediate logic network using the optimization process to create an optimized intermediate logic network. Next, the system creates an optimized first logic network based on the optimized intermediate logic network. In this way, the system indirectly uses the optimization process to efficiently optimize the first logic network.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: March 18, 2008
    Assignee: Synopsys, Inc.
    Inventor: Nan Zhuang
  • Publication number: 20070044045
    Abstract: One embodiment of the present invention provides a system that optimizes a logic network. During operation, the system receives a first logic network which defines a logical function, wherein the first logic network cannot be efficiently optimized by directly using an optimization process that preserves the logical function. Next, the system creates an intermediate logic network based on the first logic network, wherein the intermediate logic network defines an intermediate logical function which is different from the logical function, wherein the intermediate logic network can be efficiently optimized using the optimization process. The system then optimizes the intermediate logic network using the optimization process to create an optimized intermediate logic network. Next, the system creates an optimized first logic network based on the optimized intermediate logic network. In this way, the system indirectly uses the optimization process to efficiently optimize the first logic network.
    Type: Application
    Filed: August 19, 2005
    Publication date: February 22, 2007
    Inventor: Nan Zhuang