Patents by Inventor Nanaji Saka

Nanaji Saka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6667239
    Abstract: A method of chemical mechanical polishing of a metal damascene structure which includes an insulation layer having trenches on a wafer and a metal layer having a lower portion located in trenches of the insulation layer and an upper portion overlying the lower portion and the insulation layer is provided. The method comprises a first step of planarizing the upper portion of the metal layer and a second step of polishing the insulation layer and the lower portion of the metal layer. In the first step of planarizing the upper portion of the metal layer, the wafer and a polishing pad is urged at an applied pressure p and a relative velocity v in a contact mode between the wafer and the polishing pad to promote an increased metal removal rate. In the second, the insulation layer and the lower portion of the metal layer are polished in a steady-state mode to form individual metal lines in the trenches with minimal dishing of the metal lines and overpolishing of the insulation layer.
    Type: Grant
    Filed: January 23, 2002
    Date of Patent: December 23, 2003
    Assignee: ASML US, Inc.
    Inventors: Nanaji Saka, Jiun-Yu Lai, Hilario L. Oh
  • Publication number: 20030082904
    Abstract: A method of chemical mechanical polishing of a metal damascene structure which includes an insulation layer having trenches on a wafer and a metal layer having a lower portion located in trenches of the insulation layer and an upper portion overlying the lower portion and the insulation layer is provided. The method comprises a first step of planarizing the upper portion of the metal layer and a second step of polishing the insulation layer and the lower portion of the metal layer. In the first step of planarizing the upper portion of the metal layer, the wafer and a polishing pad is urged at an applied pressure p and a relative velocity v in a contact mode between the wafer and the polishing pad to promote an increased metal removal rate. In the second, the insulation layer and the lower portion of the metal layer are polished in a steady-state mode to form individual metal lines in the trenches with minimal dishing of the metal lines and overpolishing of the insulation layer.
    Type: Application
    Filed: January 23, 2002
    Publication date: May 1, 2003
    Applicant: ASML US, INC.
    Inventors: Nanaji Saka, Jiun-Yu Lai, Hilario L. Oh
  • Publication number: 20030045100
    Abstract: A method and apparatus for providing in-situ monitoring of the removal of materials in localized regions on a semiconductor wafer or substrate during chemical mechanical polishing (CMP) is provided. In particular, the method and apparatus of the present invention provides for detecting the differences in reflectance between the different materials within certain localized regions or zones on the surface of the wafer. The differences in reflectance are used to indicate the rate or progression of material removal in each of the certain localized zones.
    Type: Application
    Filed: December 21, 2001
    Publication date: March 6, 2003
    Applicant: Massachusetts Institute of Technology
    Inventors: Nanaji Saka, Jamie Nam, Hilario L. Oh