Patents by Inventor Nanako HIRASHITA
Nanako HIRASHITA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230215923Abstract: A nitride semiconductor device includes a substrate, a drift layer and a block layer sequentially provided above the substrate, a gate opening penetrating through a block layer and reaching a drift layer, an electron transit layer and an electron supply layer sequentially provided above the block layer and along the inner surface of the gate opening, a gate electrode provided to cover the gate opening, a source opening penetrating through an electron supply layer and an electron transit layer and reaching the block layer, a source electrode provided in the source opening, and a drain electrode on the rear surface side of the substrate. Seen in a plan view, at least part of an outline of an end of the gate opening in the longitudinal direction follows an arc or an elliptical arc.Type: ApplicationFiled: March 3, 2023Publication date: July 6, 2023Applicant: Panasonic Holdings CorporationInventors: Daisuke Shibata, Satoshi Tamura, Nanako Hirashita
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Patent number: 11621328Abstract: A nitride semiconductor device includes a substrate; a first nitride semiconductor layer above the substrate; a block layer above the first nitride semiconductor layer; a first opening penetrating through the block layer; an electron transit layer and an electron supply layer provided sequentially above the block layer and along an inner surface of the first opening; a gate electrode provided above the electron supply layer to cover the first opening; a second opening penetrating through the electron supply layer and the electron transit layer; a source electrode provided in the second opening; and a drain electrode. When the first main surface is seen in a plan view, (i) the first opening and the source electrode each are elongated in a predetermined direction, and (ii) at least part of an outline of a first end of the first opening in a longitudinal direction follows an arc or an elliptical arc.Type: GrantFiled: August 31, 2018Date of Patent: April 4, 2023Assignee: PANASONIC HOLDINGS CORPORATIONInventors: Daisuke Shibata, Satoshi Tamura, Nanako Hirashita
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Patent number: 11329175Abstract: A semiconductor relay includes: a substrate; a semiconductor layer of a direct transition type which is on the substrate and which has semi-insulating properties; a p-type semiconductor layer on at least part of the semiconductor layer; a first electrode; and a second electrode. The first electrode is electrically connected to the semiconductor layer and in contact with the p-type semiconductor layer. The second electrode is spaced apart from the first electrode and at least partially in contact with one of the semiconductor layer and the substrate, and the first electrode includes a first opening part.Type: GrantFiled: January 15, 2019Date of Patent: May 10, 2022Assignee: Panasonic Holdings CorporationInventors: Nanako Hirashita, Satoshi Tamura, Daisuke Shibata, Shinji Ujita
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Publication number: 20200411706Abstract: A semiconductor relay includes: a substrate; a semiconductor layer of a direct transition type which is on the substrate and which has semi-insulating properties; a p-type semiconductor layer on at least part of the semiconductor layer; a first electrode; and a second electrode. The first electrode is electrically connected to the semiconductor layer and in contact with the p-type semiconductor layer. The second electrode is spaced apart from the first electrode and at least partially in contact with one of the semiconductor layer and the substrate, and the first electrode includes a first opening part.Type: ApplicationFiled: January 15, 2019Publication date: December 31, 2020Applicant: Panasonic CorporationInventors: Nanako Hirashita, Satoshi Tamura, Daisuke Shibata, Shinji Ujita
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Patent number: 10818815Abstract: A semiconductor relay includes: a light-emitting element; and a light-receiving element facing the light-emitting element. The light-receiving element includes: a substrate; a semiconductor layer having a direct transition type, the semiconductor layer being disposed on the substrate and having a semi-insulating property; a first electrode having at least a part in contact with the semiconductor layer; and a second electrode having at least a part in contact with either one of the semiconductor layer and the substrate, in a position separated from the first electrode. The semiconductor layer is reduced in resistance by absorbing light from the light-emitting element.Type: GrantFiled: July 2, 2019Date of Patent: October 27, 2020Assignee: PANASONIC CORPORATIONInventors: Daisuke Shibata, Satoshi Tamura, Shinji Ujita, Nanako Hirashita, Masahiro Ogawa, Ryo Kajitani
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Publication number: 20200312964Abstract: A nitride semiconductor device includes a substrate; a first nitride semiconductor layer above the substrate; a block layer above the first nitride semiconductor layer; a first opening penetrating through the block layer; an electron transit layer and an electron supply layer provided sequentially above the block layer and along an inner surface of the first opening; a gate electrode provided above the electron supply layer to cover the first opening; a second opening penetrating through the electron supply layer and the electron transit layer; a source electrode provided in the second opening; and a drain electrode. When the first main surface is seen in a plan view, (i) the first opening and the source electrode each are elongated in a predetermined direction, and (ii) at least part of an outline of a first end of the first opening in a longitudinal direction follows an arc or an elliptical arc.Type: ApplicationFiled: August 31, 2018Publication date: October 1, 2020Applicant: Panasonic CorporationInventors: Daisuke Shibata, Satoshi Tamura, Nanako Hirashita
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Publication number: 20190326465Abstract: A semiconductor relay includes: a light-emitting element; and a light-receiving element facing the light-emitting element. The light-receiving element includes: a substrate; a semiconductor layer having a direct transition type, the semiconductor layer being disposed on the substrate and having a semi-insulating property; a first electrode having at least a part in contact with the semiconductor layer; and a second electrode having at least a part in contact with either one of the semiconductor layer and the substrate, in a position separated from the first electrode. The semiconductor layer is reduced in resistance by absorbing light from the light-emitting element.Type: ApplicationFiled: July 2, 2019Publication date: October 24, 2019Applicant: PANASONIC CORPORATIONInventors: Daisuke Shibata, Satoshi Tamura, Shinji Ujita, Nanako Hirashita, Masahiro Ogawa, Ryo Kajitani
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Patent number: 9231059Abstract: A semiconductor device includes a substrate; a carrier traveling layer formed on the substrate, made of first group III nitride semiconductor, and containing carriers traveling in a direction along a principal surface of the substrate; a barrier layer formed on the carrier traveling layer and made of second group III nitride semiconductor having a wider band gap than the first group III nitride semiconductor; and an electrode formed on the barrier layer. The device further includes a cap layer formed on the barrier layer at a side of the electrode, and made of third group III nitride semiconductor containing a mixture of single crystals and polycrystals.Type: GrantFiled: December 11, 2013Date of Patent: January 5, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Noboru Negoro, Hidekazu Umeda, Nanako Hirashita, Tetsuzo Ueda
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Patent number: 9190474Abstract: A semiconductor device includes a substrate; a carrier traveling layer formed on the substrate, made of first group III nitride semiconductor, and containing carriers traveling in a direction along a principal surface of the substrate; a barrier layer formed on the carrier traveling layer and made of second group III nitride semiconductor having a wider band gap than the first group III nitride semiconductor; and an electrode formed on the barrier layer. The device further includes a cap layer formed on the barrier layer at a side of the electrode, and made of third group III nitride semiconductor containing a mixture of single crystals and polycrystals.Type: GrantFiled: December 11, 2013Date of Patent: November 17, 2015Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Noboru Negoro, Hidekazu Umeda, Nanako Hirashita, Tetsuzo Ueda
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Publication number: 20140097433Abstract: A semiconductor device includes a substrate; a carrier traveling layer formed on the substrate, made of first group III nitride semiconductor, and containing carriers traveling in a direction along a principal surface of the substrate; a barrier layer formed on the carrier traveling layer and made of second group III nitride semiconductor having a wider band gap than the first group III nitride semiconductor; and an electrode formed on the barrier layer. The device further includes a cap layer formed on the barrier layer at a side of the electrode, and made of third group III nitride semiconductor containing a mixture of single crystals and polycrystals.Type: ApplicationFiled: December 11, 2013Publication date: April 10, 2014Applicant: Panasonic CorporationInventors: Noboru NEGORO, Hidekazu UMEDA, Nanako HIRASHITA, Tetsuzo UEDA