Patents by Inventor Nancy Ann Lynch

Nancy Ann Lynch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11226951
    Abstract: Described are devices, systems and techniques for implementing atomic memory objects in a multi-writer, multi-reader setting. In an embodiment, the devices, systems and techniques use maximum distance separable (MDS) codes, and may be specifically designed to optimize a total storage cost for a given fault-tolerance requirement. Also described is an embodiment to handle the case where some of the servers can return erroneous coded elements during a read operation.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: January 18, 2022
    Assignees: Massachusetts Institute of Technology, Northeastern University, University of Connecticut
    Inventors: Muriel Medard, Kishori Mohan Konwar, Prakash Narayana Moorthy, Nancy Ann Lynch, Erez Kantor, Alexander Allister Schwarzmann
  • Publication number: 20210191916
    Abstract: Described are devices, systems and techniques for implementing atomic memory objects in a multi-writer, multi-reader setting. In an embodiment, the devices, systems and techniques use maximum distance separable (MDS) codes, and may be specifically designed to optimize a total storage cost for a given fault-tolerance requirement. Also described is an embodiment to handle the case where some of the servers can return erroneous coded elements during a read operation.
    Type: Application
    Filed: November 23, 2020
    Publication date: June 24, 2021
    Inventors: Muriel Medard, Kishori Mohan Konwar, Prakash Narayana Moorthy, Nancy Ann Lynch, Erez Kantor, Alexander Allister Schwarzmann
  • Patent number: 10872072
    Abstract: Described are devices, systems and techniques for implementing atomic memory objects in a multi-writer, multi-reader setting. In an embodiment, the devices, systems and techniques use maximum distance separable (MDS) codes, and may be specifically designed to optimize a total storage cost for a given fault-tolerance requirement. Also described is an embodiment to handle the case where some of the servers can return erroneous coded elements during a read operation.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: December 22, 2020
    Assignees: Massachusetts Institute of Technology, Northeastern University, University of Connecticut
    Inventors: Muriel Medard, Kishori Mohan Konwar, Prakash Narayana Moorthy, Nancy Ann Lynch, Erez Kantor, Alexander Allister Schwarzmann
  • Patent number: 10735515
    Abstract: A two-layer erasure-coded fault-tolerant distributed storage system offering atomic access for read and write operations is described. In some embodiments, a class of erasure codes known as regenerating codes (e.g. minimum bandwidth regenerating codes) for storage of data in a backend layer is used to reduce a cost of backend bulk storage and helps in reducing communication cost of read operations, when a value needs to be recreated from persistent storage in the backend layer. By separating the functionality of edge layer servers and backend servers, a modular implementation for atomicity using storage-efficient erasure-codes is provided. Such a two-layer modular architecture permits protocols needed for consistency implementation to be substantially limited to the interaction between clients and an edge layer, while protocols needed to implement erasure code are substantially limited to interaction between edge and backend layers.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: August 4, 2020
    Assignee: Massachusetts Institute of Technology
    Inventors: Kishori Mohan Konwar, Prakash Narayana Moorthy, Muriel Medard, Nancy Ann Lynch
  • Publication number: 20180337996
    Abstract: A two-layer erasure-coded fault-tolerant distributed storage system offering atomic access for read and write operations is described. In some embodiments, a class of erasure codes known as regenerating codes (e.g. minimum bandwidth regenerating codes) for storage of data in a backend layer is used to reduce a cost of backend bulk storage and helps in reducing communication cost of read operations, when a value needs to be recreated from persistent storage in the backend layer. By separating the functionality of edge layer servers and backend servers, a modular implementation for atomicity using storage-efficient erasure-codes is provided. Such a two-layer modular architecture permits protocols needed for consistency implementation to be substantially limited to the interaction between clients and an edge layer, while protocols needed to implement erasure code are substantially limited to interaction between edge and backend layers.
    Type: Application
    Filed: May 22, 2018
    Publication date: November 22, 2018
    Inventors: Kishori Mohan KONWAR, Prakash NARAYANA MOORTHY, Muriel MEDARD, Nancy Ann LYNCH
  • Publication number: 20180165318
    Abstract: Described are devices, systems and techniques for implementing atomic memory objects in a multi-writer, multi-reader setting. In an embodiment, the devices, systems and techniques use maximum distance separable (MDS) codes, and may be specifically designed to optimize a total storage cost for a given fault-tolerance requirement. Also described is an embodiment to handle the case where some of the servers can return erroneous coded elements during a read operation.
    Type: Application
    Filed: December 12, 2017
    Publication date: June 14, 2018
    Inventors: Muriel Medard, Kishori Mohan Konwar, Prakash Narayana Moorthy, Nancy Ann Lynch, Erez Kantor, Alexander Allister Schwarzmann