Abstract: Observability of internal system-on-chip signals is a difficult problem and it is particularly difficult to observe and debug transactions with different clock domains. However, one embodiment provides observability of internal signals from multiple internal blocks having varying clock domains such as synchronous (common clock) and asynchronous (non common clock) domains. An embodiment provides simultaneous observability of debug data from both synchronous and asynchronous clock domains. An embodiment may also allow sending debug data from both synchronous and asynchronous domains from the SoC. One embodiment outputs internal signals on output pins of the SoC, thereby allowing transactions from one clock domain to be tracked to another clock domain and allowing for the determination of the relationship between the data of differing clock domains. Other embodiments are described herein.

Abstract: Observability of internal system-on-chip signals is a difficult problem and it is particularly difficult to observe and debug transactions with different clock domains. However, one embodiment provides observability of internal signals from multiple internal blocks having varying clock domains such as synchronous (common clock) and asynchronous (non common clock) domains. An embodiment provides simultaneous observability of debug data from both synchronous and asynchronous clock domains. An embodiment may also allow sending debug data from both synchronous and asynchronous domains from the SoC. One embodiment outputs internal signals on output pins of the SoC, thereby allowing transactions from one clock domain to be tracked to another clock domain and allowing for the determination of the relationship between the data of differing clock domains. Other embodiments are described herein.

Abstract: In a system in which individual memory banks may be under individual power control, a subsequent need for a memory bank that is currently in a low power state may be anticipated, so that the memory bank may be powered up in advance of when it is needed, to reduce or eliminate delays caused by waiting for the memory bank to power up and become operational. The anticipation may be based on accessing a predetermined location in another memory bank.

Abstract: An electronic circuit comprises at least one digital logic circuit; and a power control circuit. The power control circuit is operable to adjust the voltage of a power signal supplied to the at least one digital logic circuit in response to a change in a clock frequency provided to the at least one digital logic circuit. In a further embodiment, the power controller is operable to increase the voltage of the power signal applied to the digital logic circuit before a frequency increase is made, and is operable to decrease the voltage of the power signal applied to the digital logic circuit after a frequency decrease is made.

Abstract: In a system in which individual memory banks may be under individual power control, a subsequent need for a memory bank that is currently in a low power state may be anticipated, so that the memory bank may be powered up in advance of when it is needed, to reduce or eliminate delays caused by waiting for the memory bank to power up and become operational. The anticipation may be based on accessing a predetermined location in another memory bank.

Abstract: An external bus master (205) accesses a DRAM (207) using a memory controller (804) internal to a data processor (3) without the use of external multiplexers or any other external circuitry. The need for external multiplexers and even a dedicated integrated circuit pin for providing external control during external master initiated DRAM accesses is removed by the implementation of a circuit and technique for multiplexing row and column addresses of the DRAM internally within the data processor.

Abstract: Control over bus arbitration within a data processing system between a plurality of bus devices (101, 102) coupled by a bus (103) is performed in a user programmable manner by implementing logic circuitry that is responsive to a user programmable bit within a register (203) so that when the bit is asserted, the bus device (102) is able to maintain control over access to the external bus (103). Such a technique is useful for permitting a processor (201) to maintain mastership of an external bus (103) with respect to a direct memory access device (101) also coupled to the bus (103).

Abstract: A user may program a data processor (3) such that external master chip select accesses can be either the same or different length of time than an internal master access through the use of a control register (810). Additionally, the user can turn off the internal transfer acknowledge logic and add external transfer acknowledge logic while still using the internal chip select and write enable generation logic (8) of the data processor. This feature is user programmable on a chip select basis and provides a flexible solution which allows the user to compensate for different external master accesses without requiring external chip select and write enable logic. Therefore, overhead is conserved and efficiency is increased.

Abstract: A data processing system (10) having a bus controller (5) that uses a communication bus (22) which adapts to various system resources (7) and is capable of burst transfers. In one embodiment, the processor core (2) and system resources (7) supply control signals supplying required parameters of the next transfer. The bus controller is capable of transferring operands and/or instructions in incremental bursts from these system resources. Each transfer data burst has an associated unique access address where successive bytes of data are associated with sequential addresses and the burst increment equals the data port size. The burst capability is dependent on the ability of system resource (7) to burst data and can be inhibited with a transfer burst inhibit signal. The length of the desired data is controlled by a sizing signal from the core (2) or from cache and the increment size is supplied by the resource (7).

Abstract: A data processing system (10) having a bus controller (5) and a multiplexed communication bus (22) and provides a portion of the valid address information during the data phase. In one embodiment, in response to an address extension control signal, the bus controller (5) allocates the communication bus (22) to provide the address extension on conductors not needed for data, reducing the need for address latch circuitry. In an alternate embodiment, the bus controller (5) provides burst transfers where the processor core (2) increments a portion of each address with each data in the burst. For such burst transfers, the length of the desired data is controlled by a sizing signal (42) from the core (2) or from cache and the increment size is supplied by the system resource (7).

Abstract: In a system in which individual memory banks may be under individual power control, a subsequent need for a memory bank that is currently in a low power state may be anticipated, so that the memory bank may be powered up in advance of when it is needed, to reduce or eliminate delays caused by waiting for the memory bank to power up and become operational. The anticipation may be based on accessing a predetermined location in another memory bank.