Abstract: A metal layer is formed at high deposition rate over severe topography by a two step process including formation of a seed layer by cold deposition followed by a second portion of the metal layer deposited at a temperature approximating but below a temperature at which metal from a lower metal layer can extrude through vias reaching thereto. The seed layer is preferably limited to a thickness at which the conformality of the cold-deposited metal will not significantly increase severity of surface topography, generally about one-fourth the thickness of the hot-deposited layer. Via connections are formed without voids and a more planar metal layer surface is formed which allows formation of a protective/anti-reflective layer with good integrity while enhancing subsequent lithographic patterning, thereby eliminating alteration of metal surface chemistry by resist developers and resultant residual metal included within the severe topography.

Abstract: A method for increasing the production yield of semiconductor devices having copper metallurgy planarized by a chemical-mechanical planarization process which includes a slurry that contains a conductor passivating agent, like benzotriazole, wherein a non-oxidizing anneal is used to remove any residue which might interfere with mechanical probing of conductive lands on the substrate prior to further metallization steps. The anneal may be performed by any of several techniques including a vacuum chamber, a standard furnace or by rapid thermal annealing.

Abstract: A lithographic process for creation and replication of well-controlled surfaces of arbitrary profiles on a sub-micron scale. The surfaces are defined by a mathematical function using a binary mask, consisting partly or wholly of subresolution features, and a photoresist film of pre-specified absorption and thickness. The process comprises the steps of (a) creating a mask, (b) imaging the mask pattern on an absorbing photoresist film to a predetermined thickness, and (c) transferring the three dimensional surface to a substrate.

Abstract: The propagation of a crack from the surface of the dielectric layer of an integrated circuit, through to the underlying circuit elements, is prevented by controlling the interface between the outermost, dielectric layer or layers and the inner layer or layers of the integrated circuit construction. The interface is weakened so that a crack that encounters the interface is caused to propagate in a horizontal manner, along the interface, preventing propagation of the crack in a direction that would be harmful to the manufactured article. This is preferably accomplished with multiple layers of material, each of which is made capable of redirecting (deflecting) the crack. Deflection of the crack, and arrest of the deflected crack along the interface, is made possible by controlling the fracture resistance of the interface.

Abstract: The propagation of a crack from the surface of the dielectric layer of an integrated circuit, through to the underlying circuit elements, is prevented by controlling the interface between the outermost, dielectric layer or layers and the inner layer or layers of the integrated circuit construction. The interface is weakened so that a crack that encounters the interface is caused to propagate in a horizontal manner, along the interface, preventing propagation of the crack in a direction that would be harmful to the manufactured article. This is preferably accomplished with multiple layers of material, each of which is made capable of redirecting (deflecting) the crack. Deflection of the crack, and arrest of the deflected crack along the interface, is made possible by controlling the fracture resistance of the interface.

Abstract: A metal layer is formed at high deposition rate over severe topography by a two step process including formation of a seed layer by cold deposition followed by a second portion of the metal layer deposited at a temperature approximating but below a temperature at which metal from a lower metal layer can extrude through vias reaching thereto. The seed layer is preferably limited to a thickness at which the conformality of the cold-deposited metal will not significantly increase severity of surface topography, generally about one-fourth the thickness of the hot-deposited layer. Via connections are formed without voids and a more planar metal layer surface is formed which allows formation of a protective/anti-reflective layer with good integrity while enhancing subsequent lithographic patterning, thereby eliminating alteration of metal surface chemistry by resist developers and resultant residual metal included within the severe topography.

Abstract: A method in a plasma processing chamber for etching through a selected portion of a layer stack. The layer stack comprises a metallization layer, a first barrier layer disposed adjacent to the metallization layer, and a photoresist layer disposed above the metallization layer. The method includes etching at least partially through the first barrier layer using a high sputter component etch. The method further includes etching at least partially through the metallization layer using a low sputter component etch. The low sputter component etch has a sputter component lower than a sputter component of the high sputter component etch.

Abstract: A method is provided for forming a conductive stud and line over a surface, comprising the steps of: forming at least a first layer of material over the region on the surface whereat the conductive stud and line are to be formed; forming a layer of dual image photoresist over the material; exposing the dual image potoresist to radiation so as to form at least first and second regions exhibiting different development characteristics; developing the first region so as to expose a portion of the material; removing the exposed portion of the material so as to define the position of one of the conductive line or stud; developing the second region to expose more of the material; and removing the newly exposed portion of material so as to define the position of the other of the conductive line or stud.

Abstract: A method for detecting the endpoint in an etching process including the steps of: providing a structure to be etched including at least a first layer of material overlying a second layer of material; ablating an aperture in the first layer using a beam of coherent electromagnetic radiation so as to expose a portion of the second layer; exposing the structure to an etchant for etching the second layer; and monitoring the second layer using the ablated aperture so as to detect an endpoint for the etching process.

Abstract: Disclosed is a process for forming a planarized multilevel ship wiring structure. Starting from a substrate having thereon at least a metal stud serving as vertical wiring between two levels of metallization, a quartz layer is deposited, obtaining a non-planar structure. A thick planarizing photoactive photoresist is applied. The photoresist is converted by silylation process into a silicate having substantially the same etch rate as that of quartz. Silylation is accomplished by, for example, subjecting to resist to a bath of hexamethyldisilazane, hexamethylcyclotrisilazane, octamethylcyclotetrasilazane, N,N,dimethylaminotrimethylsilane or N,N,diethylaminotrimethylsilane, for a period of time determined by the thickness of the resist. Unwanted portions of the silylated resist and quartz are etched back at 1:1 etch rate ratio to the level of the stud.

Abstract: Disclosed is a process for forming a planarized multilevel ship wiring structure. Starting from a substrate having thereon at least a metal stud serving as vertical wiring between two levels of metallization, a quartz layer is deposited, obtaining a non-planar structure. A thick planarizing photoactive photoresist is applied. The photoresist is converted by silylation process into a silicate having substantially the same etch rate as that of quartz. Silylation is accomplished by, for example, subjecting the resist to a bath of hexamethyldisilazane, hexamethylcyclotrisilazene, octamethylcyclotetrasilazane, N,N,dimethylaminotrimethylsilane or N,N,diethylaminotrimethylsilane, for a period of time determined by the thickness of the resist. Unwanted portions of the silylated resist and quartz are etched back at 1:1 etch rate ratio to the level of the stud.