Patents by Inventor Nancy Leong
Nancy Leong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8559255Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.Type: GrantFiled: August 8, 2012Date of Patent: October 15, 2013Assignee: Spansion LLCInventors: Sung-Yong Chung, Zhizheng Liu, Yugi Mizuguchi, Xuguang Alan Wang, Yi He, Ming Kwan, Darlene Hamilton, Sung-Chul Lee, Guowei Wang, Nancy Leong
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Publication number: 20120294103Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.Type: ApplicationFiled: August 8, 2012Publication date: November 22, 2012Applicant: SPANSION LLCInventors: Sung-Yong Chung, Zhizheng Liu, Yugi Mizuguchi, Xuguang Alan Wang, Yi He, Ming Kwan, Darlene Hamilton, Sung-Chul Lee, Guowei Wang, Nancy Leong
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Patent number: 8264898Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.Type: GrantFiled: June 9, 2011Date of Patent: September 11, 2012Assignee: Spansion LLCInventors: Sung-Yong Chung, Zhizheng Liu, Yugi Mizuguchi, Xuguang Alan Wang, Yi He, Ming Kwan, Darlene Hamilton, Sung-Chul Lee, Guowei Wang, Nancy Leong
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Publication number: 20110235412Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.Type: ApplicationFiled: June 9, 2011Publication date: September 29, 2011Applicant: Spansion LLCInventors: Sung-Yong Chung, Zhizheng Liu, Yugi Mizuguchi, Xuguang Alan Wang, Yi He, Ming Kwan, Darlene Hamilton, Sung-Chul Lee, Guowei Wang, Nancy Leong
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Patent number: 7986562Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.Type: GrantFiled: December 30, 2009Date of Patent: July 26, 2011Assignee: Spansion LLCInventors: Sung-Yong Chung, Zhizheng Liu, Yugi Mizuguchi, Xuguang Alan Wang, Yi He, Ming Kwan, Darlene Hamilton, Sung-Chul Lee, Guowei Wang, Nancy Leong
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Publication number: 20100103732Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.Type: ApplicationFiled: December 30, 2009Publication date: April 29, 2010Applicant: SPANSION LLCInventors: Sung-Yong Chung, Zhizheng Liu, Yugi Mizuguchi, Xuguang Alan Wang, Yi He, Ming Kwan, Darlene Hamilton, Sung-Chul Lee, Guowei Wang, Nancy Leong
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Patent number: 7679967Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.Type: GrantFiled: December 21, 2007Date of Patent: March 16, 2010Assignee: Spansion LLCInventors: Sung-Yong Chung, Zhizheng Liu, Yugi Mizuguchi, Xuguang Alan Wang, Yi He, Ming Kwan, Darlene Hamilton, Sung-Chul Lee, Guowei Wang, Nancy Leong
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Publication number: 20090161462Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.Type: ApplicationFiled: December 21, 2007Publication date: June 25, 2009Applicant: SPANSION LLCInventors: Sung-Yong Chung, Zhizheng Liu, Yugi Mizuguchi, Xuguang Alan Wang, Yi He, Ming Kwan, Darlene Hamilton, Sung-Chul Lee, Guowei Wang, Nancy Leong
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Patent number: 7453724Abstract: A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory cells in the array. A first group of memory cells to be programmed is identified from the plurality of memory cells in the programming window. The first group of memory cells is programmed and a programming state of the first group of memory cells is verified.Type: GrantFiled: October 31, 2007Date of Patent: November 18, 2008Assignee: Spansion, LLCInventors: Aaron Lee, Hounien Chen, Sachit Chandra, Nancy Leong, Guowei Wang
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Patent number: 7443732Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.Type: GrantFiled: September 20, 2005Date of Patent: October 28, 2008Assignee: Spansion LLCInventors: Tiao-Hua Kuo, Nancy Leong, Nian Yang, Guowei Wang, Aaron Lee, Sachit Chandra, Michael A. VanBuskirk, Johnny Chen, Darlene Hamilton, Binh Quang Le
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Patent number: 7433228Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element having at least two charge storage areas for storing at least two independent charges, a source region and a drain region. The method includes designating at least one memory cell as a high-speed memory cell and pre-conditioning the high-speed memory cells by placing a first of the at least two charge storage areas into a programmed state, and subsequently enabling the programming on the second area with much higher rate.Type: GrantFiled: September 20, 2005Date of Patent: October 7, 2008Assignee: Spansion LLCInventors: Tiao-Hua Kuo, Nancy Leong, Hounien Chen, Sachit Chandra, Nian Yang
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Patent number: 7423915Abstract: A non-volatile memory, such as a Flash memory, is configured to perform a random multi-page read operation. The memory may include a core array of non-volatile memory cells and input lines for receiving an indication of the random multi-page read operation. Further, the memory may include a multi-level volatile memory coupled to the core array that is configured to simultaneously process multiple pages of data from the core array in a pipelined manner. Output lines are coupled to the multi-level volatile memory and output the pages of data from the memory device.Type: GrantFiled: January 17, 2006Date of Patent: September 9, 2008Assignee: Spansion LLCInventors: Nancy Leong, Sachit Chandra, Hounien Chen
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Publication number: 20080049516Abstract: A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory cells in the array. A first group of memory cells to be programmed is identified from the plurality of memory cells in the programming window. The first group of memory cells is programmed and a programming state of the first group of memory cells is verified.Type: ApplicationFiled: October 31, 2007Publication date: February 28, 2008Applicant: SPANSION L.L.C.Inventors: Aaron LEE, Hounien CHEN, Sachit CHANDRA, Nancy LEONG, Guowei WANG
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Patent number: 7307878Abstract: A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory cells in the array. A first group of memory cells to be programmed is identified from the plurality of memory cells in the programming window. The first group of memory cells is programmed and a programming state of the first group of memory cells is verified.Type: GrantFiled: August 29, 2005Date of Patent: December 11, 2007Assignee: Spansion LLCInventors: Aaron Lee, Hounien Chen, Sachit Chandra, Nancy Leong, Guowei Wang
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Publication number: 20070165458Abstract: A non-volatile memory, such as a Flash memory, is configured to perform a random multi-page read operation. The memory may include a core array of non-volatile memory cells and input lines for receiving an indication of the random multi-page read operation. Further, the memory may include a multi-level volatile memory coupled to the core array that is configured to simultaneously process multiple pages of data from the core array in a pipelined manner. Output lines are coupled to the multi-level volatile memory and output the pages of data from the memory device.Type: ApplicationFiled: January 17, 2006Publication date: July 19, 2007Inventors: Nancy Leong, Sachit Chandra, Hounien Chen
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Publication number: 20070064464Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.Type: ApplicationFiled: September 20, 2005Publication date: March 22, 2007Inventors: Tiao-Hua Kuo, Nancy Leong, Nian Yang, Guowei Wang, Aaron Lee, Sachit Chandra, Michael VanBuskirk, Johnny Chen, Darlene Hamilton, Binh Le
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Publication number: 20070064480Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element having at least two charge storage areas for storing at least two independent charges, a source region and a drain region. The method includes designating at least one memory cell as a high-speed memory cell and pre-conditioning the high-speed memory cells by placing a first of the at least two charge storage areas into a programmed state, and subsequently enabling the programming on the second area with much higher rate.Type: ApplicationFiled: September 20, 2005Publication date: March 22, 2007Inventors: Tiao-Hua Kuo, Nancy Leong, Hounien Chen, Sachit Chandra, Nian Yang
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Publication number: 20070035991Abstract: A method for reading a nonvolatile memory array including an array of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region, includes receiving, at an address register, a read command including an address for a memory cell in the array of memory cells and an indication regarding whether the read command is a full page read command or a partial page read command. A starting address for a page including the received address is identified, wherein the page includes multiple rows of memory cells in the array of memory cells. The address register is reset to the starting address for the page. It is determined whether all memory cells in the page are non-programmed. Data indicative of a non-programmed state of the page is output if it is determined that all memory cells in the page are non-programmed.Type: ApplicationFiled: July 27, 2005Publication date: February 15, 2007Inventors: Hounien Chen, Nancy Leong
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Patent number: 6633949Abstract: A bank selector encoder comprises a partition indicator circuit having a plurality of partition boundary indicator terminals, a plurality of inverters arranged in a plurality of columns, with each column of the inverters coupled to a respective one of a plurality of columns of ROM cells in a ROM array and a plurality of bank selector code outputs coupled to respective columns of the inverters. The partition boundary indicator terminals are capable of designating a memory partition boundary to identify an upper memory bank and a lower memory bank. The bank selector encoder is capable of generating an identifying bank selector code for each of a plurality of the predetermined memory partition boundaries. The bank selector encoder outputs code bits of a bank selector code based upon the partition boundary indicator terminals.Type: GrantFiled: June 26, 2001Date of Patent: October 14, 2003Assignees: Advanced Micro Devices, Inc., Fujitsu LimitedInventors: Tiao-Hua Kuo, Yasushi Kasa, Nancy Leong, Johnny Chen, Michael Van Buskirk
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Patent number: 6470414Abstract: A bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture comprises a memory boundary option, a bank selector encoder coupled to receive a memory partition indicator signal from the memory boundary option, and a bank selector decoder coupled to receive a bank selector code from the bank selector encoder. The decoder, upon receiving a memory address, outputs a bank selector output signal to point the memory address to either a lower memory bank or an upper memory bank in the simultaneous operation flash memory device, in dependence upon the selected memory partition boundary.Type: GrantFiled: June 26, 2001Date of Patent: October 22, 2002Assignees: Advanced Micro Devices, Inc., Fujitsu LimitedInventors: Tiao-Hua Kuo, Yasushi Kasa, Nancy Leong, Johnny Chen, Michael Van Buskirk