Abstract: An apparatus is described. The apparatus includes a flash memory chip having a self-aligned dielectric fill between pillars. The self-aligned dielectric fill extends through a polysilicon layer. The pillars have respective access transistors formed with the polysilicon layer. The self-aligned dielectric fill to electrically isolate the pillars.

Abstract: A semiconductor circuit includes multiple decks of semiconductor devices, each deck having multiple three-dimensional (3D) stacks. The semiconductor circuit has a nitride layer between the first deck and the second deck. The nitride layer has a self-aligned pillar through the nitride layer to electrically connect the first deck to the second deck. The nitride layer can have multiple sublayers, with a mirrored gradient doping, with lower doping toward the middle of the nitride layer and higher doping toward the outsides of the nitride layer that interfaces with the decks.