Patents by Inventor Nancy M Zelick
Nancy M Zelick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11631737Abstract: Embodiments of the invention include nanowire and nanoribbon transistors and methods of forming such transistors. According to an embodiment, a method for forming a microelectronic device may include forming a multi-layer stack within a trench formed in a shallow trench isolation (STI) layer. The multi-layer stack may comprise at least a channel layer, a release layer formed below the channel layer, and a buffer layer formed below the channel layer. The STI layer may be recessed so that a top surface of the STI layer is below a top surface of the release layer. The exposed release layer from below the channel layer by selectively etching away the release layer relative to the channel layer.Type: GrantFiled: December 24, 2014Date of Patent: April 18, 2023Assignee: Intel CorporationInventors: Sanaz K. Gardner, Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Jack T. Kavalieros, Chandra S. Mohapatra, Anand S. Murthy, Nadia M. Rahhal-Orabi, Nancy M. Zelick, Tahir Ghani
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Patent number: 10756198Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.Type: GrantFiled: August 16, 2017Date of Patent: August 25, 2020Assignee: Intel CorporationInventors: Gilbert Dewey, Niloy Mukherjee, Matthew Metz, Jack T. Kavalieros, Nancy M. Zelick, Robert S. Chau
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Patent number: 10249490Abstract: A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.Type: GrantFiled: March 14, 2017Date of Patent: April 2, 2019Assignee: Intel CorporationInventors: Niti Goel, Robert S. Chau, Jack T. Kavalieros, Benjamin Chu-Kung, Matthew V. Metz, Niloy Mukherjee, Nancy M. Zelick, Gilbert Dewey, Willy Rachmady, Marko Radosavljevic, Van H. Le, Ravi Pillarisetty, Sansaptak Dasgupta
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Publication number: 20170365681Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.Type: ApplicationFiled: August 16, 2017Publication date: December 21, 2017Inventors: Gilbert DEWEY, Niloy MUKHERJEE, Matthew METZ, Jack T. KAVALIEROS, Nancy M. ZELICK, Robert S. CHAU
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Publication number: 20170323963Abstract: An embodiment includes a device comprising: a fin structure including an upper portion and a lower portion, the upper portion having a bottom surface directly contacting an upper surface of the lower portion; wherein (a) the lower portion is included in a trench having an aspect ratio (depth to width) of at least 2:1; (b) the bottom surface has a bottom maximum width and the upper surface has an upper maximum width that is greater the bottom maximum width; (c) the bottom surface covers a middle portion of the upper surface but does not cover lateral portions of the upper surface; and (d) the upper portion includes an upper III-V material and the lower portion includes a lower III-V material different from the upper III-V material. Other embodiments are described herein.Type: ApplicationFiled: December 23, 2014Publication date: November 9, 2017Inventors: Sanaz K. GARDNER, Willy RACHMADY, Matthew V. METZ, Gilbert DEWEY, Jack T. KAVALIEROS, Chandra S. MOHAPATRA, Anand S. MURTHY, Nadia RAHHAL-ORABI, Nancy M. ZELICK, Tahir GHANI
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Publication number: 20170317187Abstract: An embodiment includes a device comprising: first and second fins adjacent one another and each including channel and subfin layers, the channel layers having bottom surfaces directly contacting upper surfaces of the subfin layers; wherein (a) the bottom surfaces are generally coplanar with one another and are generally flat; (b) the upper surfaces are generally coplanar with one another and are generally flat; and (c) the channel layers include an upper material and the subfin layers include a lower III-V material different from the upper III-V material. Other embodiments are described herein.Type: ApplicationFiled: December 23, 2014Publication date: November 2, 2017Inventors: Sanaz K. GARDNER, Willy RACHMADY, Matthew V. METZ, Gilbert DEWEY, Jack T. KAVALIEROS, Chandra S. MOHAPATRA, Anand S. MURTHY, Nadia RAHHAL-ORABI, Nancy M. ZELICK, Marc C. FRENCH, Tahir GHANI
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Patent number: 9768269Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.Type: GrantFiled: September 18, 2014Date of Patent: September 19, 2017Assignee: Intel CorporationInventors: Gilbert Dewey, Niloy Mukherjee, Matthew Metz, Jack T. Kavalieros, Nancy M. Zelick, Robert S. Chau
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Publication number: 20170263706Abstract: Embodiments of the invention include nanowire and nanoribbon transistors and methods of forming such transistors. According to an embodiment, a method for forming a microelectronic device may include forming a multi-layer stack within a trench formed in a shallow trench isolation (STI) layer. The multi-layer stack may comprise at least a channel layer, a release layer formed below the channel layer, and a buffer layer formed below the channel layer. The STI layer may be recessed so that a top surface of the STI layer is below a top surface of the release layer. The exposed release layer from below the channel layer by selectively etching away the release layer relative to the channel layer.Type: ApplicationFiled: December 24, 2014Publication date: September 14, 2017Inventors: Sanaz K. GARDNER, Willy RACHMADY, Matthew V. METZ, Gilbert DEWEY, Jack T. KAVALIEROS, Chandra S. MOHAPATRA, Anand S. MURTHY, Nadia M. RAHHAL-ORABI, Nancy M. ZELICK, Tahir GHANI
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Publication number: 20170186598Abstract: A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.Type: ApplicationFiled: March 14, 2017Publication date: June 29, 2017Inventors: Niti Goel, Robert S. CHAU, Jack T. KAVALIEROS, Benjamin CHU-KUNG, Matthew V. METZ, Niloy MUKHERJEE, Nancy M. ZELICK, Gilbert DEWEY, Willy RACHMADY, Marko RADOSAVLJEVIC, Van H. LE, Ravi PILLARISETTY, Sansaptak DASGUPTA
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Patent number: 9680013Abstract: A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.Type: GrantFiled: September 5, 2013Date of Patent: June 13, 2017Assignee: Intel CorporationInventors: Stephen M. Cea, Roza Kotlyar, Jack T. Kavalieros, Martin D. Giles, Tahir Ghani, Kelin J. Kuhn, Markus Kuhn, Nancy M. Zelick
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Patent number: 9640537Abstract: A single fin or a pair of co-integrated n- and p- type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.Type: GrantFiled: September 27, 2013Date of Patent: May 2, 2017Assignee: Intel CorporationInventors: Niti Goel, Robert S. Chau, Jack T. Kavalieros, Benjamin Chu-Kung, Matthew V. Metz, Niloy Mukherjee, Nancy M. Zelick, Gilbert Dewey, Willy Rachmady, Marko Radosavljevic, Van H. Le, Ravi Pillarisetty, Sansaptak Dasgupta
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Publication number: 20160211263Abstract: A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.Type: ApplicationFiled: September 27, 2013Publication date: July 21, 2016Inventors: Niti GOEL, Robert S. CHAU, Jack T. KAVALIEROS, Benjamin CHU-KUNG, Matthew V. METZ, Niloy MUKHERJEE, Nancy M. ZELICK, Gilbert DEWEY, Willy RACHMADY, Marko RADOSAVLJEVIC, Van H. LE, Ravi PILLARISETTY, Sansaptak DASGUPTA
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Patent number: 9391181Abstract: An embodiment concerns forming an EPI film on a substrate where the EPI film has a different lattice constant from the substrate. The EPI film and substrate may include different materials to collectively form a hetero-epitaxial device having, for example, a Si and/or SiGe substrate and a III-V or IV film. The EPI film may be one of multiple EPI layers or films and the films may include different materials from one another and may directly contact one another. Further, the multiple EPI layers may be doped differently from another in terms of doping concentration and/or doping polarity. One embodiment includes creating a horizontally oriented hetero-epitaxial structure. Another embodiment includes a vertically oriented hetero-epitaxial structure. The hetero-epitaxial structures may include, for example, a bipolar junction transistor, heterojunction bipolar transistor, thyristor, and tunneling field effect transistor among others. Other embodiments are described herein.Type: GrantFiled: December 21, 2012Date of Patent: July 12, 2016Assignee: Intel CorporationInventors: Benjamin Chu-Kung, Van H. Le, Robert S. Chau, Sansaptak Dasgupta, Gilbert Dewey, Niti Goel, Jack T. Kavalieros, Matthew V. Metz, Niloy Mukherjee, Ravi Pillarisetty, Willy Rachmady, Marko Radosavljevic, Han Wui Then, Nancy M. Zelick
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Publication number: 20160190319Abstract: Non-planar semiconductor devices having multi-layered compliant substrates and methods of fabricating such non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a lower portion composed of a first semiconductor material with a first lattice constant (L1), and has an upper portion composed of a second semiconductor material with a second lattice constant (L2). A cladding layer is disposed on the upper portion, but not on the lower portion, of the semiconductor fin. The cladding layer is composed of a third semiconductor material with a third lattice constant (L3), wherein L3>L2>L1. A gate stack is disposed on a channel region of the cladding layer. Source/drain regions are disposed on either side of the channel region.Type: ApplicationFiled: September 27, 2013Publication date: June 30, 2016Inventors: JACK T. KAVALIEROS, MARKO RADOSAVLJEVIC, MATTHEW V. METZ, HAN WUI THEN, BENJAMIN CHU-KUNG, VAN H. LE, NILOY MUKHERJEE, SANSAPTAK DASGUPTA, RAVI PILLARISETTY, GILBERT DEWEY, ROBERT S. CHAU, NANCY M. ZELICK, WILLY RACHMADY
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Publication number: 20150001644Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.Type: ApplicationFiled: September 18, 2014Publication date: January 1, 2015Inventors: Gilbert Dewey, Niloy Mukherjee, Matthew Metz, Jack T. Kavalieros, Nancy M. Zelick, Robert S. Chau
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Patent number: 8878363Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.Type: GrantFiled: June 26, 2009Date of Patent: November 4, 2014Assignee: Intel CorporationInventors: Gilbert Dewey, Niloy Mukherjee, Matthew Metz, Jack T. Kavalieros, Nancy M. Zelick, Robert S. Chau
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Publication number: 20140070273Abstract: A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.Type: ApplicationFiled: September 5, 2013Publication date: March 13, 2014Inventors: Stephen M. Cea, Roza Kotlyar, Jack T. Kavalieros, Martin D. Giles, Tahir Ghani, Kelin J. Kuhn, Markus Kuhn, Nancy M. Zelick
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Patent number: 8558279Abstract: A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.Type: GrantFiled: September 23, 2010Date of Patent: October 15, 2013Assignee: Intel CorporationInventors: Stephen M. Cea, Roza Kotlyar, Jack T. Kavalieros, Martin D. Giles, Tahir Ghani, Kelin J. Kuhn, Markus Kuhn, Nancy M. Zelick
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Patent number: 8211772Abstract: Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.Type: GrantFiled: December 23, 2009Date of Patent: July 3, 2012Assignee: Intel CorporationInventors: Jack T. Kavalieros, Nancy M. Zelick, Been-Yih Jin, Markus Kuhn, Stephen M. Cea
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Publication number: 20120074464Abstract: A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.Type: ApplicationFiled: September 23, 2010Publication date: March 29, 2012Inventors: Stephen M. Cea, Roza Kotlyar, Jack T. Kavalieros, Martin D. Giles, Tahir Ghani, Kelin J. Kuhn, Markus Kuhn, Nancy M. Zelick