Patents by Inventor Nancy M Zelick

Nancy M Zelick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7960794
    Abstract: A non-planar tri-gate p-MOS transistor structure with a strained channel region and a non-planar tri-gate integrated strained complimentary metal-oxide-semiconductor (CMOS) structure are described. A relaxed Si1-x Gex layer is formed on the silicon-on-isolator (SOI) substrate. The relaxed Si1-x Gex layer is patterned and subsequently etched to form a fin on the oxide. The compressively stressed Si1-y Gey layer, having the Ge content y higher than the Ge content x in the relaxed Si1-x Gex layer, is epitaxially grown on the fin. The Si1-y Gey layer covers the top and two sidewalls of the fin. The compressive stress in the Si1-y Gey layer substantially increases the hole mobility in a channel of the non-planar tri-gate p-MOS transistor structure.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: June 14, 2011
    Assignee: Intel Corporation
    Inventors: Brian S Doyle, Suman Datta, Been-Yih Jin, Nancy M Zelick, Robert Chau
  • Patent number: 7348284
    Abstract: A non-planar tri-gate p-MOS transistor structure with a strained channel region and a non-planar tri-gate integrated strained complimentary metal-oxide-semiconductor (CMOS) structure are described. A relaxed Si1-x Gex layer is formed on the silicon-on-isolator (SOI) substrate. The relaxed Si1-x Gex layer is patterned and subsequently etched to form a fin on the oxide. The compressively stressed Si1-y Gey layer, having the Ge content y higher than the Ge content x in the relaxed Si1-xGex layer, is epitaxially grown on the fin. The Si1-y Gey layer covers the top and two sidewalls of the fin. The compressive stress in the Si1-y Gey layer substantially increases the hole mobility in a channel of the non-planar tri-gate p-MOS transistor structure.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: March 25, 2008
    Assignee: Intel Corporation
    Inventors: Brian S Doyle, Suman Datta, Been-Yih Jin, Nancy M Zelick, Robert Chau