Patents by Inventor Nancy Ngar Sze Chan

Nancy Ngar Sze Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Loopback testing with phase alignment of a sampling clock at a test receiver apparatus
    Patent number: 8468398
    Abstract: Methods and test receiver apparatus are provided for loopback testing of a unidirectional physical layer device. The disclosed methods and test receiver apparatus allow for the phase of a sampling clock implemented at the test receiver apparatus to be aligned with the phase of a test data signal.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: June 18, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kunlun Kenny Jiang, Nancy Ngar Sze Chan
  • LOOPBACK TESTING WITH PHASE ALIGNMENT OF A SAMPLING CLOCK AT A TEST RECEIVER APPARATUS
    Publication number: 20120192043
    Abstract: Methods and test receiver apparatus are provided for loopback testing of a unidirectional physical layer device. The disclosed methods and test receiver apparatus allow for the phase of a sampling clock implemented at the test receiver apparatus to be aligned with the phase of a test data signal.
    Type: Application
    Filed: January 20, 2011
    Publication date: July 26, 2012
    Applicant: ATI TECHNOLOGIES ULC
    Inventors: Kunlun Kenny JIANG, Nancy Ngar Sze CHAN
  • Method and apparatus for parallel in serial out transmission
    Patent number: 6563485
    Abstract: A method and apparatus for providing serial transmission of a parallel input is accomplished by a parallel input serial output transmitter that includes a shift register operably coupled to receive a parallel input and to provide data serially to a gating circuit. The gating circuit, based on the state of the data it receives, generates a drive signal which causes a switching circuit to route current from first and second current sources to a third current source over different paths to produce a serial output. A bias circuit is coupled to the switching circuit to bias the serial output to a desired level.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: May 13, 2003
    Assignee: ATI Technologies, Inc.
    Inventors: Edward Chak Cheung Ho, Nancy Ngar Sze Chan, Hugh Hin-Poon Chow
  • Method and apparatus for parallel in serial out transmission
    Publication number: 20020158833
    Abstract: A method and apparatus for providing serial transmission of a parallel input is accomplished by a parallel input serial output transmitter that includes a shift register operably coupled to receive a parallel input and to provide data serially to a gating circuit. The gating circuit, based on the state of the data it receives, generates a drive signal which causes a switching circuit to route current from first and second current sources to a third current source over different paths to produce a serial output. A bias circuit is coupled to the switching circuit to bias the serial output to a desired level.
    Type: Application
    Filed: April 30, 2001
    Publication date: October 31, 2002
    Inventors: Edward Chak Cheung Ho, Nancy Ngar Sze Chan, Hugh Hin-Poon Chow