Patents by Inventor Nancy Pratt
Nancy Pratt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9946620Abstract: A memory built-in self test (“BIST”) system comprises: a controller; a single port memory engine coupled to one or more single port memories; and a non-single port memory engine coupled to one or more non-single port memories. The controller receives operation codes (“op-codes”) for testing a plurality of memory types. An output of the controller is coupled to inputs of the single port memory engine and the non-single port memory engine. The controller generates test instructions based on the received op-codes. The single port memory engine and the non-single port memory engine interpret the test instructions to test the one or more single port memories and the one or more non-single port memories.Type: GrantFiled: February 1, 2016Date of Patent: April 17, 2018Assignee: Invecas, Inc.Inventors: Kevin W. Gorman, Thomas Chadwick, Nancy Pratt
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Patent number: 9865361Abstract: A memory diagnostic system comprises a test engine and a miscompare logic. The test engine provides test instructions with expected data to a memory under test (“MUT”). The MUT processes such test patterns and outputs the results of such test patterns as stored data. The miscompare logic has local miscompare logics and a global miscompare logic. Each of the local miscompare logics compares a predefined range of bits of the expected data with a corresponding predefined range of bits of the stored data. One or more miscompare flags are generated for one or more miscompares determined by the local miscompare logics. The global miscompare logic monitors the one or more miscompare flags. When a total number of the miscompare flags exceeds a threshold number, the global miscompare logic generates a pause signal to the local miscompare logics to capture a current state of the local miscompare logics.Type: GrantFiled: April 27, 2016Date of Patent: January 9, 2018Assignee: Invecas, Inc.Inventors: Thomas Chadwick, Kevin W. Gorman, Nancy Pratt
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Publication number: 20170316837Abstract: A memory diagnostic system comprises a test engine and a miscompare logic. The test engine provides test instructions with expected data to a memory under test (“MUT”). The MUT processes such test patterns and outputs the results of such test patterns as stored data. The miscompare logic has local miscompare logics and a global miscompare logic. Each of the local miscompare logics compares a predefined range of bits of the expected data with a corresponding predefined range of bits of the stored data. One or more miscompare flags are generated for one or more miscompares determined by the local miscompare logics. The global miscompare logic monitors the one or more miscompare flags. When a total number of the miscompare flags exceeds a threshold number, the global miscompare logic generates a pause signal to the local miscompare logics to capture a current state of the local miscompare logics.Type: ApplicationFiled: April 27, 2016Publication date: November 2, 2017Inventors: Thomas Chadwick, Kevin W. Gorman, Nancy Pratt
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Patent number: 9799413Abstract: A fuse controller comprises: a fuse bay, a bus, an engine, and an interface. The fuse bay stores repair and setting information for a plurality of fuse domains in a linked-list data structure. The engine manages the linked-list data structure. The engine also is coupled to the fuse domains via the bus. The interface is coupled to the engine and receives commands and data for operating the engine.Type: GrantFiled: February 1, 2016Date of Patent: October 24, 2017Assignee: Invecas, Inc.Inventors: Kevin W. Gorman, Thomas Chadwick, Nancy Pratt
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Publication number: 20160224450Abstract: A memory built-in self test (“BIST”) system comprises: a controller; a single port memory engine coupled to one or more single port memories; and a non-single port memory engine coupled to one or more non-single port memories. The controller receives operation codes (“op-codes”) for testing a plurality of memory types. An output of the controller is coupled to inputs of the single port memory engine and the non-single port memory engine. The controller generates test instructions based on the received op-codes. The single port memory engine and the non-single port memory engine interpret the test instructions to test the one or more single port memories and the one or more non-single port memories.Type: ApplicationFiled: February 1, 2016Publication date: August 4, 2016Inventors: Kevin W. Gorman, Thomas Chadwick, Nancy Pratt
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Publication number: 20160224451Abstract: A fuse controller comprises: a fuse bay, a bus, an engine, and an interface. The fuse bay stores repair and setting information for a plurality of fuse domains in a linked-list data structure. The engine manages the linked-list data structure. The engine also is coupled to the fuse domains via the bus. The interface is coupled to the engine and receives commands and data for operating the engine.Type: ApplicationFiled: February 1, 2016Publication date: August 4, 2016Inventors: Kevin W. Gorman, Thomas Chadwick, Nancy Pratt
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Publication number: 20080068073Abstract: A digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.Type: ApplicationFiled: November 9, 2007Publication date: March 20, 2008Inventors: Nancy Pratt, Sebastian Ventrone
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Publication number: 20070288787Abstract: A digital system and a method for operating the same. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.Type: ApplicationFiled: August 10, 2007Publication date: December 13, 2007Inventors: Nancy Pratt, Sebastian Ventrone
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Publication number: 20070028151Abstract: A method and system for supporting simultaneous operation of operating systems on a single integrated circuit. The system includes a supervisory operating system (SOS) managing execution of instructions, each instruction being executable under one of the operating systems; registers grouped into multiple sets of registers, each set maintaining an identity of one of the operating systems; and a dispatcher capable of dispatching an instruction and a tag attached to the instruction, the tag identifying one of the operating systems and the instruction to be executed under the identified operating system to access one of the registers. One or more of the registers are utilized when the instruction is executed, and are included in a single set of the multiple sets of registers. The single set maintains the identity of the operating system identified by the tag, and each of the one or more registers includes an identifier matching the tag.Type: ApplicationFiled: July 29, 2005Publication date: February 1, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Laura Miller, Nancy Pratt, Sebastian Ventrone
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Publication number: 20060082398Abstract: A digital system and a method for operating the same. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.Type: ApplicationFiled: January 27, 2006Publication date: April 20, 2006Inventors: Nancy Pratt, Sebastian Ventrone
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Publication number: 20050096862Abstract: A method and system for identifying logic function areas, which make up a virtual machine, that are affected by specific testcases. A Hardware Descriptor Language (HDL) is used to create a software model of the virtual machine. A simulator compiles and analyzes the HDL model, and creates a matrix scoreboard identifying logic function areas in the virtual machine. A complete list of testcases is run on the virtual machine while a monitor correlates each testcase with affected logic function areas to fill in the matrix scoreboard. When a subsequent test failure occurs, either because of a modification to a logic function area, or the execution of a new test, all logic function areas that are affected, either directly or indirectly, are identified.Type: ApplicationFiled: November 4, 2003Publication date: May 5, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jason Norman, Nancy Pratt, Sebastian Ventrone