Patents by Inventor Nanda Siddaiah

Nanda Siddaiah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Sparse tree adder circuit
    Patent number: 7509368
    Abstract: An adder circuit is provided that includes a propagate and generate circuit stage to provide propagate and generate signals, a plurality of carry-merge stages to provide carry signals based on the propagate and generate signals and a conditional sum generator to provide conditional sums based on the propagate and generate signals. The conditional sum generator includes ripple carry gates and XOR logic gates. The adder circuit also includes a plurality of multiplexers to receive the carry signals and the conditional sums and to provide an output based on the input signals.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: March 24, 2009
    Assignee: Intel Corporation
    Inventors: Mark A. Anders, Sanu K. Mathew, Nanda Siddaiah, Sapumal Wijeratne
  • Sparse tree adder circuit
    Publication number: 20060253523
    Abstract: An adder circuit is provided that includes a propagate and generate circuit stage to provide propagate and generate signals, a plurality of carry-merge stages to provide carry signals based on the propagate and generate signals and a conditional sum generator to provide conditional sums based on the propagate and generate signals. The conditional sum generator includes ripple carry gates and XOR logic gates. The adder circuit also includes a plurality of multiplexers to receive the carry signals and the conditional sums and to provide an output based on the input signals.
    Type: Application
    Filed: May 9, 2005
    Publication date: November 9, 2006
    Inventors: Mark Anders, Sanu Mathew, Nanda Siddaiah, Sapumal Wijeratne