Abstract: One or more devices, systems, and/or methods are provided. In an example of the techniques presented herein, an oscillator comprises a voltage controlled oscillator configured to generate an output clock based on a drive signal, a frequency to voltage converter having a time constant and configured to generate a feedback voltage having a decay cycle based on the time constant and a frequency based on a frequency of the output clock, and an integrator configured to generate the drive signal based on an integration of the feedback voltage and a reference voltage.

Abstract: An oscillation circuit includes resistors with tap points for high/low reference voltages. An RC network coupled in parallel with the resistors includes a first capacitor to vary a first voltage input and a second capacitor to generate a second voltage input. A first comparator alternately compares the voltage inputs with the low reference voltage to generate oscillation outputs. A PTAT current DAC supplies an injection current to a resistor of the series of resistors that variably modulates the reference voltages. A second comparator alternately compares the voltage inputs with the high reference voltage and controls generation of an adaptive bias current to first comparator near a switching threshold voltage range thereof. A chop switch matrix alternately flips voltage reference inputs to input terminals of first comparator. A multiplexer alternately inverts a polarity of the oscillation outputs in concert with alternately flipping the voltage reference inputs by the chop switch matrix.

Abstract: In examples, an apparatus for sensing current comprises a power transistor; a sense transistor coupled to the power transistor; and an offset addition circuit coupled to the power transistor and the sense transistor, the offset addition circuit comprising a first pair of transistors and a differential amplifier. The apparatus also comprises a cascode amplifier circuit coupled to the offset addition circuit, the cascode amplifier circuit comprising a second pair of transistors, and a gain trim circuit coupled to the cascode amplifier circuit, the gain trim circuit including another differential amplifier and a third transistor. The apparatus further includes an analog-to-digital converter (ADC) coupled to the gain trim circuit and storage coupled to the ADC.

Abstract: In examples, an apparatus for sensing current comprises a power transistor; a sense transistor coupled to the power transistor; and an offset addition circuit coupled to the power transistor and the sense transistor, the offset addition circuit comprising a first pair of transistors and a differential amplifier. The apparatus also comprises a cascode amplifier circuit coupled to the offset addition circuit, the cascode amplifier circuit comprising a second pair of transistors, and a gain trim circuit coupled to the cascode amplifier circuit, the gain trim circuit including another differential amplifier and a third transistor. The apparatus further includes an analog-to-digital converter (ADC) coupled to the gain trim circuit and storage coupled to the ADC.

Abstract: A VBOOST generator includes, for example, a voltage regulator for generating a first power rail VX between the supply voltage VCC and ground. A clock generator is arranged to generate a clock signal oscillating between the supply voltage VCC and the voltage VCC?VX. A charge pump is arranged to couple the voltage VCC?VX to a first terminal of an on-substrate flyback capacitor during a first half-cycle of the first clock signal and is arranged to couple the voltage VCC to the first terminal of the flyback capacitor during a second half-cycle of the first clock signal. A pin is coupled to the substrate couples the voltage VCC+VX developed on a second terminal of the flyback capacitor during the second half-cycle of the first clock signal to an external bucket capacitor. A second charge pump is optionally included to increase the charging capacity of the VBOOST generator.

Abstract: A VBOOST generator includes, for example, a voltage regulator for generating a first power rail VX between the supply voltage VCC and ground. A clock generator is arranged to generate a clock signal oscillating between the supply voltage VCC and the voltage VCC?VX. A charge pump is arranged to couple the voltage VCC?VX to a first terminal of an on-substrate flyback capacitor during a first half-cycle of the first clock signal and is arranged to couple the voltage VCC to the first terminal of the flyback capacitor during a second half-cycle of the first clock signal. A pin is coupled to the substrate couples the voltage VCC+VX developed on a second terminal of the flyback capacitor during the second half-cycle of the first clock signal to an external bucket capacitor. A second charge pump is optionally included to increase the charging capacity of the VBOOST generator.

Abstract: The disclosure provides an over-current protection circuit. A signal generating block in the over-current protection circuit generates one or more input voltages, a summed voltage and an average voltage in response to one or more differential voltages. A control block generates one or more control signals in response to the one or more input voltages and the average voltage. An analog control loop block generates an initiation signal in response to the summed voltage and an output voltage. A phase control logic block generates one or more PWM (pulse width modulated) signals in response to the initiation signal and the one or more control signals.

Abstract: Undershoot reduction circuitry includes, for example, a first comparator, a second comparator, and a controller. The first comparator is operable for comparing an indication of a power supply voltage output against a first threshold. The second comparator is operable for comparing an indication of the power supply voltage output against a second threshold. The controller is operable for generating a first power control signal to raise the power supply voltage output when the indication of the power supply voltage output has a first slope and crosses the first threshold and to lower the power supply voltage output when the indication of the power supply voltage output has an opposite slope and crosses the second threshold.

Abstract: The disclosure provides an over-current protection circuit. A signal generating block in the over-current protection circuit generates one or more input voltages, a summed voltage and an average voltage in response to one or more differential voltages. A control block generates one or more control signals in response to the one or more input voltages and the average voltage. An analog control loop block generates an initiation signal in response to the summed voltage and an output voltage. A phase control logic block generates one or more PWM (pulse width modulated) signals in response to the initiation signal and the one or more control signals.

Abstract: Undershoot reduction circuitry includes, for example, a first comparator, a second comparator, and a controller. The first comparator is operable for comparing an indication of a power supply voltage output against a first threshold. The second comparator is operable for comparing an indication of the power supply voltage output against a second threshold. The controller is operable for generating a first power control signal to raise the power supply voltage output when the indication of the power supply voltage output has a first slope and crosses the first threshold and to lower the power supply voltage output when the indication of the power supply voltage output has an opposite slope and crosses the second threshold.

Abstract: A circuit for charging a capacitive load to a reference voltage in a capacitive sensor measurement circuit includes a reference buffer, a boost buffer, and drive logic. The reference buffer and the boost buffer are coupled with the capacitive load to be charged. The boost buffer first charges the capacitive load towards the reference voltage at a first rate of charging, and then ceases charging. The reference buffer subsequently continues charging at a slower second rate to settle the voltage across the capacitive load to within a tolerable range of the reference voltage.

Abstract: An apparatus, method and system are described for providing a low power replica biased regulated supply voltage without the size requirements of using a large resistor coupled between the source of a master transistor and ground. Instead, a source of a replica transistor diode may be biased with a bias voltage, and the gate and drain of the diode may be biased with a current bias. Additional descriptions provide the supply voltage without the size requirements of a resistor coupled between a source of one or more pass transistors and ground. Instead, the source of the pass transistor(s) may be biased with a “leaker” current.

Abstract: A circuit for charging a capacitive load to a reference voltage in a capacitive sensor measurement circuit includes a reference buffer, a boost buffer, and drive logic. The reference buffer and the boost buffer are coupled with the capacitive load to be charged. The boost buffer first charges the capacitive load towards the reference voltage at a first rate of charging, and then ceases charging. The reference buffer subsequently continues charging at a slower second rate to settle the voltage across the capacitive load to within a tolerable range of the reference voltage.

Abstract: An apparatus, method and system are described for providing a low power replica biased regulated supply voltage without the size requirements of using a large resistor coupled between the source of a master transistor and ground. Instead, a source of a replica transistor diode may be biased with a bias voltage, and the gate and drain of the diode may be biased with a current bias. Additional descriptions provide the supply voltage without the size requirements of a resistor coupled between a source of one or more pass transistors and ground. Instead, the source of the pass transistor(s) may be biased with a “leaker” current.