Patents by Inventor Nandakumar Sampath

Nandakumar Sampath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7715410
    Abstract: In a data-packet processor, a configurable queuing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeuing of the selected packet identifiers.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: May 11, 2010
    Assignee: MIPS Technologies, Inc.
    Inventors: Mario Nemirovsky, Enric Musoll, Stephen Melvin, Narendra Sankar, Nandakumar Sampath, Adolfo Nemirovsky
  • Patent number: 7551626
    Abstract: In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeueing of the selected packet identifiers.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: June 23, 2009
    Assignee: MIPS Technologies, Inc.
    Inventors: Mario Nemirovsky, Enric Musoll, Stephen Melvin, Narendra Sankar, Nandakumar Sampath, Adolfo Nemirovsky
  • Patent number: 7280548
    Abstract: A system is provided for enabling a non-speculative pre-fetch operation for processing instructions to be performed in the background ahead of immediate packet processing by a packet processor. The system comprises a packet-management unit for accepting data packets and enqueuing them for processing, a processor unit for processing the data packets, a processor core memory for holding context registers and functional units for processing, a memory for holding a plurality of instruction threads and a software-configurable hardware table for relating queues to pointers to beginnings of instruction threads. The packet-management unit selects an available context in the processor core for processing of a data packet, consults the table, and communicates the pointer to the processor, enabling the processor to perform the non-speculative pre-fetch for instructions.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: October 9, 2007
    Assignee: MIPS Technologies, Inc.
    Inventors: Nandakumar Sampath, Enrique Musoll, Stephen Melvin, Mario Nemirovsky
  • Publication number: 20060215670
    Abstract: A system is provided for enabling a non-speculative pre-fetch operation for processing instructions to be performed in the background ahead of immediate packet processing by a packet processor. The system comprises a packet-management unit for accepting data packets and enqueuing them for processing, a processor unit for processing the data packets, a processor core memory for holding context registers and functional units for processing, a memory for holding a plurality of instruction threads and a software-configurable hardware table for relating queues to pointers to beginnings of instruction threads. The packet-management unit selects an available context in the processor core for processing of a data packet, consults the table, and communicates the pointer to the processor, enabling the processor to perform the non-speculative pre-fetch for instructions.
    Type: Application
    Filed: April 6, 2006
    Publication date: September 28, 2006
    Applicant: MIPS Technologies, Inc.
    Inventors: Nandakumar Sampath, Enrique Musoll, Stephen Melvin, Mario Nemirovsky
  • Publication number: 20060159104
    Abstract: In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeueing of the selected packet identifiers.
    Type: Application
    Filed: March 23, 2006
    Publication date: July 20, 2006
    Inventors: Mario Nemirovsky, Enric Musoll, Stephen Melvin, Narendra Sankar, Nandakumar Sampath, Adolfo Nemirovsky
  • Publication number: 20060153197
    Abstract: In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeueing of the selected packet identifiers.
    Type: Application
    Filed: February 23, 2006
    Publication date: July 13, 2006
    Inventors: Mario Nemirovsky, Enric Musoll, Stephen Melvin, Narendra Sankar, Nandakumar Sampath, Adolfo Nemirovsky
  • Patent number: 7058064
    Abstract: In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeueing of the selected packet identifiers.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: June 6, 2006
    Assignee: MIPS Technologies, Inc.
    Inventors: Mario Nemirovsky, Enric Musoll, Stephen Melvin, Narendra Sankar, Nandakumar Sampath, Adolfo Nemirovsky
  • Patent number: 7042887
    Abstract: A system is provided for enabling a non-speculative pre-fetch operation for processing instructions to be performed in the background ahead of immediate packet processing by a packet processor. The system comprises a packet-management unit for accepting data packets and en-queuing them for processing, a processor unit for processing the data packets, a processor core memory for holding context registers and functional units for processing, a memory for holding a plurality of instruction threads and a software-configurable hardware table for relating queues to pointers to beginnings of instruction threads. The packet-management unit selects an available context in the processor core for processing of a data packet, consults the table, and communicates the pointer to the processor, enabling the processor to perform the non-speculative pre-fetch for instructions.
    Type: Grant
    Filed: July 5, 2001
    Date of Patent: May 9, 2006
    Assignee: MIPS Technologies, Inc.
    Inventors: Nandakumar Sampath, Enrique Musoll, Stephen Melvin, Mario Nemirovsky
  • Patent number: 7035998
    Abstract: A pipelined multistreaming processor has an instruction source, a first cluster of a plurality of streams fetching instructions from the instruction source, a second cluster of a plurality of streams fetching instructions from the instruction source, dedicated instruction queues for individual streams in each cluster, a first dedicated dispatch stage in the first cluster for dispatching instructions to execution units, and a second dedicated dispatch stage in the second cluster for selecting and dispatching instructions to execution units. The processor is characterized in that the clusters operate independently, with the dedicated dispatch stage taking instructions only from the instruction queues in the individual clusters to which the dispatch stages are dedicated. In preferred embodiments there are dedicated fetch and dispatch stages for streams in the clusters, and dedicated execution units to which instructions may be dispatched.
    Type: Grant
    Filed: November 3, 2000
    Date of Patent: April 25, 2006
    Assignee: MIPS Technologies, Inc.
    Inventors: Mario Nemirovsky, Stephen W. Melvin, Nandakumar Sampath, Enrique Musoll, Hector Urdaneta
  • Publication number: 20020021707
    Abstract: A system is provided for enabling a non-speculative pre-fetch operation for processing instructions to be performed in the background ahead of immediate packet processing by a packet processor. The system comprises a packet-management unit for accepting data packets and en-queuing them for processing, a processor unit for processing the data packets, a processor core memory for holding context registers and functional units for processing, a memory for holding a plurality of instruction threads and a software-configurable hardware table for relating queues to pointers to beginnings of instruction threads. The packet-management unit selects an available context in the processor core for processing of a data packet, consults the table, and communicates the pointer to the processor, enabling the processor to perform the non-speculative pre-fetch for instructions.
    Type: Application
    Filed: July 5, 2001
    Publication date: February 21, 2002
    Inventors: Nandakumar Sampath, Enrique Musoll, Stephen Melvin, Mario Nemirovsky
  • Publication number: 20010043610
    Abstract: In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeueing of the selected packet identifiers.
    Type: Application
    Filed: December 14, 2000
    Publication date: November 22, 2001
    Inventors: Mario Nemirovsky, Enric Musoll, Stephen Melvin, Narendra Sankar, Nandakumar Sampath, Adolfo Nemirovsky