Abstract: Aspects of the invention include techniques for improving the accuracy of access-limited neural network inference in low-voltage regimes. A non-limiting example method includes training a first machine learning model to perform input transformation for reducing low-voltage bit errors for a deep neural network operating in a low-voltage regime. The training includes inputting training data into the first machine learning model such that, in response, the first machine learning model produces transformed training data; inputting the transformed training data into a clean machine learning model and into perturbed machine learning models, the perturbed machine learning models being generated by applying random bit errors to the clean machine learning model; and optimizing the first machine learning model based on a comparison of output of the clean machine learning model and of the perturbed machine learning models compared to groundtruth labels for the training data.

Abstract: An input transformation function that transforms input data for a second machine learning system is learned using a first machine learning system, the learning being based on minimizing a summation of a task loss and a post-activation density loss. The input data is transformed using the learned input transformation function to alter the post-activation density to reduce an amount of energy consumed for an inferencing task and the inferencing task is carried out on the transformed input data using the second machine learning system.

Abstract: A method (and structure and computer product) to optimize an operation in a Neural Network Accelerator (NNAccel) that includes a hierarchy of neural network layers as computational stages for the NNAccel and a configurable hierarchy of memory modules including one or more on-chip Static Random-Access Memory (SRAM) modules and one or more Dynamic Random-Access Memory (DRAM) modules, where each memory module is controlled by a plurality of operational parameters that are adjustable by a controller of the NNAcc. The method includes detecting bit error rates of memory modules currently being used by the NNAccel and determining, by the controller, whether the detected bit error rates are sufficient for a predetermined threshold value for an accuracy of a processing of the NNAccel. One or more operational parameters of one or more memory modules are dynamically changed by the controller to move to a higher accuracy state when the accuracy is below the predetermined threshold value.

Abstract: A system and method for determining reliability-aware runtime optimal processor configuration can integrate soft and hard error data into a single metric, referred to as the balanced reliability metric (BRM), by using statistical dimensionality reduction techniques. The BRM can be used to not only adjust processor voltage to optimize overall reliability but also to adjust the number of on-cores to further optimize overall processor reliability. In some implementations, both coarse-grained actuations, based on optimal core count, and fine-grained actuations, based on optimal processor voltage (Vdd), may be used, where feedback control can recursively re-compute soft and hard error data based on a new configuration, until convergence at an optimal configuration.

Abstract: Applications on different processing elements have different characteristics such as latency versus bandwidth sensitivity, memory level parallelism, different memory access patterns and the like. Interference between applications due to contention at different sources leads to different effects on performance and is quantified. A method for contention-aware resource provisioning in heterogeneous processors includes receiving stand-alone performance statistics for each processing element for a given application. Multi-core performance slowdown can be computed from the received stand-alone performance statistics. When a request to provision an application on the heterogeneous processors is received, application performance requirements of the application can be determined and a bandwidth for the application can be provisioned based on the application performance requirements and the computed multi-core performance slowdown parameter.

Abstract: A system and method for determining reliability-aware runtime optimal processor configuration can integrate soft and hard error data into a single metric, referred to as the balanced reliability metric (BRM), by using statistical dimensionality reduction techniques. The BRM can be used to not only adjust processor voltage to optimize overall reliability but also to adjust the number of on-cores to further optimize overall processor reliability. In some implementations, both coarse-grained actuations, based on optimal core count, and fine-grained actuations, based on optimal processor voltage (Vdd), may be used, where feedback control can recursively re-compute soft and hard error data based on a new configuration, until convergence at an optimal configuration.

Abstract: Applications on different processing elements have different characteristics such as latency versus bandwidth sensitivity, memory level parallelism, different memory access patterns and the like. Interference between applications due to contention at different sources leads to different effects on performance and is quantified. A method for contention-aware resource provisioning in heterogeneous processors includes receiving stand-alone performance statistics for each processing element for a given application. Multi-core performance slowdown can be computed from the received stand-alone performance statistics. When a request to provision an application on the heterogeneous processors is received, application performance requirements of the application can be determined and a bandwidth for the application can be provisioned based on the application performance requirements and the computed multi-core performance slowdown parameter.