Patents by Inventor Nandini Ramani

Nandini Ramani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7023444
    Abstract: A rendering unit positions a supertile so that it intersects a primitive. The rendering unit repeatedly walks over bins of the supertile, applying a layer of texture to the bins of the supertile in each iteration of said repeated walking. The rendering unit advances to the next texture layer after having applied the current texture layer to each candidate bin of the supertile. The results of each texture layer application to the bins may be stored in a texture accumulation buffer. The size of the supertile corresponds to the size of the texture accumulation buffer. After applying a last layer of texture to the bins of the supertile, the supertile may be advanced to a new position. The rendering unit traverses the primitive with the supertile so that the union of areas visited by the supertile covers the primitive.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: April 4, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Brian D. Emberling, Michael G. Lavelle, Assana M. Fard, Nandini Ramani, David C. Kehlet, Michael A. Wasserman, Ewa M. Kubalska, Mark E Pascual
  • Patent number: 6975317
    Abstract: A graphics system and method for rendering a plurality of triangles. Information regarding the triangle may first be received. The method may then determine the longest edge or major edge of the triangle and also determine the direction or axis of the longest edge of the triangle. The method may then perform edge walking on the major edge (e.g., along the axis of the major edge) of the triangle, followed by span walking. The edge walking is preferably always performed on the major or longest edge of the triangle, prior to the span walking, and regardless of the orientation of the major edge of the triangle. This operates to load balance the edge walker and the span walker for the plurality of triangles.
    Type: Grant
    Filed: March 12, 2002
    Date of Patent: December 13, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Patrick Shehane, Michael G. Lavelle, Mark E. Pascual, Wing-Cheong Tang, Nandini Ramani
  • Patent number: 6963342
    Abstract: A system and method for assigning operations to multiple pipelines in a graphics system is disclosed. The graphics system may include an arbitration unit coupled to a plurality of calculation pipelines. The arbitration unit is operable to provide graphics operations to selected ones of the calculation pipelines. Each of the calculation pipelines is operable to perform a graphics operation. Each of the calculation pipelines may include digital logic and/or a processing element for performing the graphics operations. An operation may be assigned to a pipeline if the pipeline is performing a low latency operation. A low latency operation may comprise an operation that is performed by one of the calculation pipelines in less time than a pre-determined number of clock cycles.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: November 8, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Mark E. Pascual, Michael G. Lavelle, Nandini Ramani, Patrick Shehane
  • Patent number: 6947057
    Abstract: A graphics system and method for displaying lines on a display device. The system may comprise a sample buffer, a rendering unit and a sample-to-pixel calculation unit. The rendering unit may (a) generate a plurality of sample positions in a two-dimensional space, (b) determine a sample normal distance for each of the sample positions with respect to a line defined by the line-draw command, (c) assign sample values to the sample positions based on the sample normal distance of each of the sample positions, and (d) store the sample values in the sample buffer. The sample-to-pixel calculation unit may read sample values from the sample buffer, filter them to determine a pixel value, and transmit the pixel value to the display device. The rendering unit may render the line sample values with a narrower width to pre-compensate for the line-expanding effect of the filtering performed by the sample-to-pixel calculation unit.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: September 20, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Scott R. Nelson, Michael F. Deering, Nandini Ramani, Mark Tian, Patrick Shehane, Kevin Tang
  • Patent number: 6943791
    Abstract: A system and method are disclosed for utilizing a Z slope test to select polygons that may be candidates for multiple storage methods. The method may calculate the absolute Z slope from vertex data and compare the calculated value with a specified threshold value. In some embodiments, for polygons that have an absolute Z slope less than the threshold value, parameter values may be rendered for only one sample position of multiple neighboring sample positions. The parameter values rendered for the one sample position may then be stored in multiple memory locations that correspond to the multiple neighboring sample positions. In some embodiments, storing parameter values in multiple memory locations may be achieved in a single write transaction. In some embodiments, utilization of the Z slope test method may be subject to user input and in other embodiments may be a dynamic decision controlled by the graphics system.
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: September 13, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Mark E. Pascual, Michael G. Lavelle, Michael F. Deering, Nandini Ramani
  • Patent number: 6940514
    Abstract: A system and method are disclosed for a rasterization pipeline with a parallel initialization path that may provide an increased rate of triangle processing. The edge walker, span walker, and sample generator modules of a rasterization pipeline may be modified to enable the next primitive in the sequence of primitives to be initialized, while the current primitive is processed. Consequently, these two processes that were done in series may now be done in parallel. Data transmitted between modules may be separated into initialization data (data the module needs to define a primitive) and primitive data (the processed output of each module). The second path is for additional initialization data, which allows each of these modules to receive the initialization data for the next primitive, while processing the primitive data for the current primitive.
    Type: Grant
    Filed: April 26, 2004
    Date of Patent: September 6, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Michael A. Wasserman, Elena M. Ing, Vannessa M. Nhan, Nandini Ramani, Charles P. Chang
  • Patent number: 6924820
    Abstract: A system and method for rasterizing and rendering graphics data is disclosed. Vertices may be grouped to form primitives such as triangles, which are rasterized using two-dimensional arrays of samples bins. To overcome fragmentation problems, the system's sample evaluation hardware may be configured to over-evaluate samples each clock cycle. Since a number of the samples will typically not survive evaluation because they will be outside the primitive being rendered, the remaining surviving samples may be combined into sets, with one set being forwarded to subsequent pipeline stages each clock cycle in order to attempt to keep the pipeline utilization high.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: August 2, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Nandini Ramani, David C. Kehlet, Michael G. Lavelle, Mark E. Pascual, Ewa M. Kubalska, Yi-Ming Tian
  • Patent number: 6900803
    Abstract: A graphics system and method are disclosed that may optimize the rate of pixel generation to match the rate at which a memory may be designed to receive pixel data. If a memory is configured to store multiple pixels substantially simultaneously, it may be advantageous to render an equivalent number of pixels substantially simultaneously and at the same rate. An edge walker that utilizes multiple sets of accumulators to generate multiple scan lines substantially simultaneously and a span walker that utilizes multiple sets of accumulators to render multiple pixel values substantially simultaneously is described.
    Type: Grant
    Filed: March 12, 2002
    Date of Patent: May 31, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Patrick Shehane, Michael G. Lavelle, Mark E. Pascual, Wing-Cheong Tang, Nandini Ramani
  • Patent number: 6867778
    Abstract: A system and method for rendering a polygon, such as a triangle. The method may comprise receiving geometry data (or vertex data) defining vertices of the polygon. The method may compute initial vertex x,y values at end points proximate to each of the vertices of the polygon, and a slope value along each edge of the polygon. The computed slope may be a quantized slope value having a first number of bits of precision. The first number of bits of precision may produce inaccuracies for interpolated x,y values computed at the end points of an edge of the polygon. The method may then interpolate x,y values along each respective edge of the polygon using the computed slope along the respective edge of the polygon. Finally the method may store final x,y values for each respective edge of the polygon. The final x,y values comprise the interpolated x,y values for non-end points of the respective edge, and the computed initial vertex x,y values for each of the end points of the respective edge.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: March 15, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Wing-Cheong Tang, Michael G. Lavelle, Mark E. Pascual, Patrick Shehane, Nandini Ramani
  • Patent number: 6831653
    Abstract: A system and method for packing pixels together to provide a increased fill rate in a frame buffer hardware in the graphics system. The graphics system may be configured to receive and rasterize graphics data at a faster cycle rate than the system's frame buffer memory fill rate. The output from the rasterization hardware may be stored in a FIFO memory that is configured to selectively shift pixels in order to improve fill rate performance. The FIFO memory may be configured to ensure that the pixels meet certain criteria in order to prevent page faults and interleave conflicts that could reduce the fill rate. The FIFO memory may also be configured to remove empty cycles that occur as a result of the pixel packing.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: December 14, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: David Kehlet, Nandini Ramani, Yan Yan Tang, Roger W. Swanson
  • Patent number: 6831645
    Abstract: One embodiment of a method of performing a font operation involves receiving a set of font data identifying a font operation to be performed. If a first font data unit in the set indicates that a first coordinate should be a background color and transparent background is enabled, the method involves outputting an enable for a second font data unit in the set. The second font data unit indicates that a second coordinate should be a foreground color. The enable for the second coordinate is output instead of a disable for the first coordinate. If instead the first font data unit in the set indicates that the first coordinate should be a background color and transparent background is disabled, the method may involve outputting a disable for the first coordinate.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: December 14, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Wing-Cheong Tang, Michael G. Lavelle, Nandini Ramani
  • Patent number: 6803916
    Abstract: A system and method for rasterizing and rendering graphics data is disclosed. Vertices may be grouped to form primitives such as triangles, which are rasterized using two-dimensional arrays of samples bins. Individual samples may be selected from the bins according to different criteria such as memory bank allocation to improve utilization of the system's rendering pipeline. Since the arrays may have more bins than the number of evaluation units in the rendering pipeline, the samples from the bins may be stored to FIFO memories to allow invalid or empty samples (those outside the primitive being rendered) to be removed. The samples may then be filtered to form pixels that are displayable to form an image on a display device.
    Type: Grant
    Filed: May 18, 2001
    Date of Patent: October 12, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Nandini Ramani, David C. Kehlet, Ewa M. Kubalska, Michael G. Lavelle, Michael A. Wasserman, Kevin Tang, Yan Yan Tang
  • Publication number: 20040183807
    Abstract: A rendering unit positions a supertile so that it intersects a primitive. The rendering unit repeatedly walks over bins of the supertile, applying a layer of texture to the bins of the supertile in each iteration of said repeated walking. The rendering unit advances to the next texture layer after having applied the current texture layer to each candidate bin of the supertile. The results of each texture layer application to the bins may be stored in a texture accumulation buffer. The size of the supertile corresponds to the size of the texture accumulation buffer. After applying a last layer of texture to the bins of the supertile, the supertile may be advanced to a new position. The rendering unit traverses the primitive with the supertile so that the union of areas visited by the supertile covers the primitive.
    Type: Application
    Filed: March 20, 2003
    Publication date: September 23, 2004
    Inventors: Brian D. Emberling, Michael G. Lavelle, Assana M. Fard, Nandini Ramani, David C. Kehlet, Michael A. Wasserman, Ewa M. Kubalska, Mark E. Pascual
  • Patent number: 6795080
    Abstract: A graphics system configured to apply multiple layers of texture information to batches of primitives. The graphics system collects primitives into a batch that share a common set of texture layers to be applied. The batch is limited so that the total estimate size of the batch is less than or equal to a storage capacity of a texture accumulation buffer. The graphics system stores samples (or fragments) corresponding to the batch primitives in the texture accumulation buffer between the application of successive texture layers.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: September 21, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Michael G. Lavelle, David C. Kehlet, Michael A. Wasserman, Nandini Ramani, Ranjit S. Oberoi
  • Publication number: 20040174364
    Abstract: The method for line patterning may include receiving line data for a first line. The line data for the first line may include an original starting point and an original endpoint. The first line may be divided into one or more line segments, which may include generating a new starting point and a new endpoint for one or more of the one or more line segments. The new line segments may then be rasterized from the new endpoint to the new starting point. In other words, each line segment may be rasterized from right to left, thus avoiding problems associated with multiple consecutive accesses of pixel addresses in the pixel buffer. The original or intended line pattern of the line is preserved since the zeros and ones are drawn or rendered in their appropriate locations as if they were being drawn left to right, even though they are actually rasterized from right to left.
    Type: Application
    Filed: March 3, 2003
    Publication date: September 9, 2004
    Inventors: Patrick D. Shehane, Michael G. Lavelle, Mark E. Pascual, Wing-Cheong Tang, Nandini Ramani
  • Patent number: 6784894
    Abstract: A graphics system configured to operate on a collection of vertices to determine mappings from an initial order to secondary and tertiary ordering. The initial order corresponds to the ordering of the vertices in an input buffer. The secondary (tertiary) ordering corresponds to the ordering of the vertices along a triangle major (minor) axis. The graphics system computes horizontal and vertical displacements along edges of the triangle in the initial ordering, and uses the signs of the horizontal displacements and vertical displacements to access a mapping table which determines the mappings. The mappings may be used to rasterize the triangle in terms of pixels (or samples).
    Type: Grant
    Filed: May 18, 2001
    Date of Patent: August 31, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Michael W. Schimpf, Michael G. Lavelle, Mark E. Pascual, Nandini Ramani
  • Patent number: 6731300
    Abstract: A graphics system may be configured to render anti-aliased dots in terms of samples and to generate pixels by filtering the samples. The pixels are supplied to one or more display devices. The means used to generate the samples may perform the computation of radial distance at positions on a grid in a rendering coordinate space, and interpolate estimates for the radial distances of samples around the dot as needed based on the radii at the grid positions.
    Type: Grant
    Filed: May 18, 2001
    Date of Patent: May 4, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Nandini Ramani, Michael A. Wasserman, Michael G. Lavelle, Mark E. Pascual, Kevin Tang, Daniel M. Chao
  • Publication number: 20030174133
    Abstract: A graphics system and method for rendering a plurality of triangles. Information regarding the triangle may first be received. The method may then determine the longest edge or major edge of the triangle and also determine the direction or axis of the longest edge of the triangle. The method may then perform edge walking on the major edge (e.g., along the axis of the major edge) of the triangle, followed by span walking. The edge walking is preferably always performed on the major or longest edge of the triangle, prior to the span walking, and regardless of the orientation of the major edge of the triangle. This operates to load balance the edge walker and the span walker for the plurality of triangles.
    Type: Application
    Filed: March 12, 2002
    Publication date: September 18, 2003
    Inventors: Patrick Shehane, Michael G. Lavelle, Mark E. Pascual, Wing-Cheong Tang, Nandini Ramani
  • Publication number: 20030174130
    Abstract: A graphics system and method are disclosed that may optimize the rate of pixel generation to match the rate at which a memory may be designed to receive pixel data. If a memory is configured to store multiple pixels substantially simultaneously, it may be advantageous to render an equivalent number of pixels substantially simultaneously and at the same rate. An edge walker that utilizes multiple sets of accumulators to generate multiple scan lines substantially simultaneously and a span walker that utilizes multiple sets of accumulators to render multiple pixel values substantially simultaneously is described.
    Type: Application
    Filed: March 12, 2002
    Publication date: September 18, 2003
    Inventors: Patrick Shehane, Michael G. Lavelle, Mark E. Pascual, Wing-Cheong Tang, Nandini Ramani
  • Publication number: 20030169252
    Abstract: A system and method are disclosed for utilizing a Z slope test to select polygons that may be candidates for multiple storage methods. The method may calculate the absolute Z slope from vertex data and compare the calculated value with a specified threshold value. In some embodiments, for polygons that have an absolute Z slope less than the threshold value, parameter values may be rendered for only one sample position of multiple neighboring sample positions. The parameter values rendered for the one sample position may then be stored in multiple memory locations that correspond to the multiple neighboring sample positions. In some embodiments, storing parameter values in multiple memory locations may be achieved in a single write transaction. In some embodiments, utilization of the Z slope test method may be subject to user input and in other embodiments may be a dynamic decision controlled by the graphics system.
    Type: Application
    Filed: March 11, 2002
    Publication date: September 11, 2003
    Inventors: Mark E. Pascual, Michael G. Lavelle, Michael F. Deering, Nandini Ramani