Abstract: A dual path ring oscillator core includes three dual path inverters, each having a first inverter and a second inverter. Within the first inverter, one transistor is coupled to a first output of a previous dual path inverter, while another transistor is coupled to a second output of the previous dual path inverter. Within the second inverter, one transistor is coupled to the second output of the previous dual path inverter, while another transistor is coupled to the previous dual path inverter's first output. A first and a final dual path inverter are analogously coupled. A transient pulse will not propagate through successive dual path inverter stages. A dual to single path converter is coupled to receive signals output by the final dual path inverter. If a transient signal appears at a dual to single path converter input, stray output node capacitance maintains a correct output signal value.

Abstract: A dual path ring oscillator core includes three dual path inverters, each having a first inverter and a second inverter. Within the first inverter, one transistor is coupled to a first output of a previous dual path inverter, while another transistor is coupled to a second output of the previous dual path inverter. Within the second inverter, one transistor is coupled to the second output of the previous dual path inverter, while another transistor is coupled to the previous dual path inverter's first output. A first and a final dual path inverter are analogously coupled. A transient pulse will not propagate through successive dual path inverter stages. A dual to single path converter is coupled to receive signals output by the final dual path inverter. If a transient signal appears at a dual to single path converter input, stray output node capacitance maintains a correct output signal value.

Abstract: A single-event upset tolerant sense latch circuit for sense amplifiers is disclosed. The single-event upset tolerant sense latch circuit includes a first set of isolation transistors, a second set of isolation transistors, a first set of dual-path inverters, a second set of dual-path inverters, and an isolation transistor. The first set of isolation transistors is coupled to a first bitline, and the second set of isolation transistors is coupled to a second bitline. The second bitline is complementary to the first bitline. The first set of dual-path inverters is coupled to the first set of isolation transistors, and the first set of dual-path inverters includes a first transistor connected to a second transistor in series along with a third transistor connected to a fourth transistor in series.

Abstract: A single-event upset tolerant sense latch circuit for sense amplifiers is disclosed. The single-event upset tolerant sense latch circuit includes a first set of isolation transistors, a second set of isolation transistors, a first set of dual-path inverters, a second set of dual-path inverters, and an isolation transistor. The first set of isolation transistors is coupled to a first bitline, and the second set of isolation transistors is coupled to a second bitline. The second bitline is complementary to the first bitline. The first set of dual-path inverters is coupled to the first set of isolation transistors, and the first set of dual-path inverters includes a first transistor connected to a second transistor in series along with a third transistor connected to a fourth transistor in series.

Abstract: A data processing apparatus has a number of data processors connected in a series by data lines so that data signals are processed in a preceding processor and communicated to a succeeding processor in the series. The apparatus has a number of control elements, where a control element has first and second inputs receiving processor status signals and an output sending a signal to enable processing. The control element output assumes a certain output state only if both inputs assume the state. The output, having assumed the state, holds the state, despite one of the inputs not holding the state, only if a certain one of the inputs does hold the state.

Abstract: A clocking system for complex electronic devices is created in an hierarchial manner whereby the master clock pulse is provided to a plurality of digital pulse aligners which in turn provide phase aligned clock signals at the field replaceable unit level to either a slave clock or a digital phase aligner. The slave clock or the digital phase aligner at the field replaceable unit level in turn provides an aligned clock pulse to a timing node on respective chips. A third level of the hierarchy provides similarly aligned pulses to individual using-circuits on the chips of the system. The digital phase aligner, aligning the output pulse at the timing node of the next level with the reference pulses being provided to the digital phase aligner at each level, insures that the timing pulses arriving at the utilizing circuits are synchronously aligned with clock pulses of the master clock.

Abstract: A clock distribution system for a data processing system is implemented in CMOS technology wherein a full-swing differential clock signal is converted to a low-voltage swing differential clock signal by a driver's circuit and then returned to a full-swing differential clock signal at each receiver circuit.

Abstract: A clock distribution system for a data processing system is implemented in CMOS technology wherein a full-swing differential clock signal is converted to a low-voltage swing differential clock signal by a driver's circuit and then returned to a full-swing differential clock signal at each receiver circuit.

Abstract: A dynamically switchable clock system having a symmetrical output signal includes a frequency doubler which couples the input frequency to provide greater resolution and synchronization of an output signal to an input signal in the frequency divider and the facility to handle odd divides as even divides at double frequency, a counter controlled by a divisor select signal, first and second compare circuits which compare against the preprogrammed count for division, the compare circuits receiving an input from the divisor select circuits, and having outputs to a counter reset line and to an output clock S/R latch which provides the frequency divided symmetrical output signal.

Abstract: A resonant clocking system is described which utilizes a feedback clock signal from the master clock node on a clocked chip and wherein the feedback clock signal is detected with a phase detector to determine the relevant phasing of the transmitted and the feedback received clock signals. An electronically controllable delay element is disposed within the transmission path of the clock signal on both the transmission leg and the return leg so that equal amounts of delay time may be added to the flight time in each direction. The delay may be electronically controlled to bring a "Transmitted Clock" pulse and a "Received Clock" pulse into phase. By insuring that the delay time for the entire transmission of the circuit by a particular clock pulse is an even number of cycle times, the master clock node on the clocked chip also may be controlled to be in phase with the "Transmitted Clock" pulse signal.

Abstract: Groups of DCVS (Differential Cascode Voltage Switch) circuits are interconnected by single-track data transfer connections. Each group contains one or more DCVS tree circuits, through which data signals propagate only on dual-track connections. In each group, at least one DCVS tree circuit is configured as an input boundary tree, and at least one tree circuit is configured as an output boundary tree. All data inputs externally applied to a group, are transferred only through input boundary trees of the group, and all data outputs transferred out of a group leave the group only through output boundary trees of the group. If a group has only a single tree, that tree serves as input and output boundary tree of the group. Each input boundary tree of each group has one or more associated primary shift register latch (SRL) circuits through which all external data inputs to that tree are transferred. Such external data inputs are received through the single-track connections mentioned above.

Abstract: Disclosed is a basic DCVS (differential cascode voltage switch) tree construct, which can be used as a uniform basis for constructing DCVS logic circuits, register-latch circuits and circuits which can be conditioned individually to function as either or both DCVS logic and register-latches. In addition to logic and load sections that may be identical to corresponding sections of prior art DCVS trees, this construct contains gating elements for providing unique functions of isolation, precharge support and latch input coupling. The isolation function is used to electrically isolate the logic and load sections from each other, so that each section can be made to operate in a mode which is independent of the other section. The precharge support function allows precharging of circuits in the logic section without involvement of the load section. The latch input coupling function allows signals to be applied to and latched in the load section from a source other than the respective logic section.

Abstract: A basic tree construction, from which differential cascode voltage switch (DCVS) circuits having variable logic personality can be formed, contains n (>2) rows of differentially associated semiconductor device pairs spanned by n pairs of complementary input conductor leads, and a load circuit coupled to drain terminals of devices in the nth row. The nth row contains 2 device pairs and each other row contains 2.sup.i-1 device pairs (i=1, 2, . . . , n-1). Connections between source and drain terminals of devices in successive rows are predefined from the 1st to the n-1st row and variably definable between the n-1st and nth rows. Connections between input conductors and device gate terminals are predefined in each row other than the nth row, and variably definable in the nth row. Upon selectively defining a set of variable connections relative to the n-1st and nth rows the logic personality of the tree is selected to conform to any one of all possible functions of n variables.

Abstract: A microword generation mechanism is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword generation mechanism includes programmable logic array means responsive to the processor instructions for producing the appropriate microword sequences. The microword generation mechanism also includes condition indicator circuitry for supplying indicator signals indicating whether the results of arithmetic and logic operations in the processor meet certain types of conditions. The microword generation mechanism further includes a condition testing programmable logic array responsive to the condition field of a conditional branch type processor instruction for testing the appropriate indicator signal or signals and causing a branch type microword sequence to be produced if the specified condition is met.

Abstract: A topological physical circuit design is utilized for the support of a Differential Cascode Voltage Switch circuit/logic technology in an Automated Placement-Wiring environment. This physical entity takes the form of a "brickwall" set of transistors in a Master Slice image which may be stored and later personalized.

Abstract: An integrated circuit mechanism is provided for coupling the separate sets of output lines from a plurality of programmable logic arrays to the same set of bus lines of plural-line signal transfer bus. This coupling mechanism includes precharge circuitry for precharging each of the bus lines during a first time interval. This coupling mechanism also includes a separate strobe signal line for each programmable logic array and circuitry for activating one of the strobe signal lines during a second time interval for selecting a particular programmable logic array. This coupling mechanism further includes a separate output buffer for each programmable logic array. Each such output buffer includes a plurality of buffer stages for individually coupling the different ones of the programmable logic array output lines to their respective bus lines.

Abstract: A clocking mechanism is provided for multiple overlapped dynamic programmable logic arrays which are used in a digital control unit wherein a sequence of control words are used to produce successive groups of control point signals. Such a control unit includes a plurality of dynamic programmable logic arrays for individually producing different ones of the control words. Each such control word includes a strobe field which is coded to identify a programmable logic array other than the one which produced it. The control unit also includes control circuitry responsive to the control words for producing the control point signals for successive machine control cycles. The control circuitry includes circuitry responsive to the strobe field in each control word for producing a strobe signal for selecting the next programmable logic array to supply a control word to the control circuitry.

Abstract: A digital data signal transfer mechanism is provided for use in large scale integration digital data processor circuitry formed on an integrated circuit chip. The signal transfer mechanism includes a plural-bit data bus formed on the integrated circuit chip for transferring plural-bit binary data signals between different locations on the chip. The signal transfer mechanism also includes plural-bit signal source circuitry and plural-bit signal destination circuitry formed on the integrated circuit chip and coupled to the plural-bit data bus for respectively supplying plural-bit data signals to and receiving plural-bit data signals from the bus.

Abstract: A tristate driver circuit is provided on an integrated circuit chip for driving a bus line or signal line located off of the chip. This circuit very rapidly charges the bus line or signal line to positive voltage level each time and just before it switches to its tristate or high impedance output condition. This eliminates the need for a pull-up resistor or pull-up transistor to be connected to the off-chip bus line or signal line.

Abstract: As a specific improvement to a previously known PLA (Programmed Logic Array) structure, formed by FET devices in serially chained charge transfer circuits, the presently disclosed "modified" PLA structure comprises a combination of: (a) level shifting circuitry, integrated into bit partitioning stages of the known structure, for reducing voltage swings in the outputs of those stages and thereby reducing spurious couplings to the following AND array stage as well as decreasing operational delays of the latter stage; (b) discrete capacitance, added at the output end of the OR array stage of the known structure, for sustaining and reinforcing charge conditions accumulated in that stage prior to readout (validation clocking) of that stage; and (c) a source of time related clocking functions coupled to stages of the modified structure, with the timing relationships selected so as to reduce operational delays of the entire structure while improving its integrity of operation.