Abstract: A single-event upset tolerant random access memory cell is disclosed. The single-event upset tolerant memory cell includes a first and second sets of access transistors along with a first and second sets of dual-path inverters. The first set of access transistors is coupled to a first bitline, and the second set of access transistors is coupled to a second bitline that is complementary to the first bitline. The first set of dual-path inverters, which is coupled to the first set of access transistors, includes a first transistor connected to a second transistor in series and a third transistor connected to a fourth transistor in series. The second set of dual-path inverters, which is coupled to the second set of access transistors, includes a fifth transistor connected to a sixth transistor in series and a seventh transistor connected to an eighth transistor in series.