Patents by Inventor Nandu Mahalingam

Nandu Mahalingam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070257211
    Abstract: The present invention provides a method for implanting ions in a substrate and a method for manufacturing an integrated circuit. The method for implanting ions in a substrate, among other steps, including placing a substrate (410) on an implant platen (405) such that a predominant axes (430) of the substrate (410) is rotated about 30 degrees to about 60 degrees or about 120 degrees to about 150 degrees offset from a radial with respect to the implant platen (405), and further wherein the substrate (410) is not tilted. The method further includes implanting ions into the substrate (410), the rotated position of the predominant axes (430) reducing shadowing.
    Type: Application
    Filed: July 2, 2007
    Publication date: November 8, 2007
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: James Bernstein, Lance Robertson, Said Ghneim, Nandu Mahalingam, Benjamin Moser
  • Patent number: 7253072
    Abstract: The present invention provides a method for implanting ions in a substrate and a method for manufacturing an integrated circuit. The method for implanting ions in a substrate, among other steps, including placing a substrate (410) on an implant platen (405) such that a predominant axes (430) of the substrate (410) is rotated about 30 degrees to about 60 degrees or about 120 degrees to about 150 degrees offset from a radial with respect to the implant platen (405), and further wherein the substrate (410) is not tilted. The method further includes implanting ions into the substrate (410), the rotated position of the predominant axes (430) reducing shadowing.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: August 7, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: James D. Bernstein, Lance S. Robertson, Said Ghneim, Nandu Mahalingam, Benjamin Moser
  • Publication number: 20060154411
    Abstract: The present invention teaches the formation of CMOS transistors using interfacial nitrogen at the interface between the lightly doped extension regions and an overlying insulating layer in combination with a capping layer of silicon nitride, both prior to the final source/drain anneal. Doses and energies may be increased for the P-channel lightly-doped drain, source and drain regions. The resulting transistors exhibit desirably high drive current and low off-state leakage current and overlap capacitance.
    Type: Application
    Filed: March 9, 2006
    Publication date: July 13, 2006
    Inventors: Haowen Bu, Brian Hornung, P.R. Chidambaram, Amitabh Jain, Rajesh Khamankar, Nandu Mahalingam, Srinivansan Chakravarthi
  • Publication number: 20050255683
    Abstract: The present invention provides a method for implanting ions in a substrate and a method for manufacturing an integrated circuit. The method for implanting ions in a substrate, among other steps, including placing a substrate (410) on an implant platen (405) such that a predominant axes (430) of the substrate (410) is rotated about 30 degrees to about 60 degrees or about 120 degrees to about 150 degrees offset from a radial with respect to the implant platen (405), and further wherein the substrate (410) is not tilted. The method further includes implanting ions into the substrate (410), the rotated position of the predominant axes (430) reducing shadowing.
    Type: Application
    Filed: December 7, 2004
    Publication date: November 17, 2005
    Applicant: Texas Instruments Incorporated
    Inventors: James Bernstein, Lance Robertson, Said Ghneim, Nandu Mahalingam, Benjamin Moser
  • Publication number: 20050059260
    Abstract: The present invention teaches the formation of CMOS transistors using interfacial nitrogen at the interface between the lightly doped extension regions and an overlying insulating layer in combination with a capping layer of silicon nitride, both prior to the final source/drain anneal. Doses and energies may be increased for the P-channel lightly-doped drain, source and drain regions. The resulting transistors exhibit desirably high drive current and low off-state leakage current and overlap capacitance.
    Type: Application
    Filed: March 26, 2004
    Publication date: March 17, 2005
    Inventors: Haowen Bu, Brian Hornung, P.R. Chidambaram, Amitabh Jain, Rajesh Khamankar, Nandu Mahalingam, Srinivansan Chakravarthi