Abstract: A memory controller and an MCU chip are provided by the present application. The memory controller adds a second memory controller to conventional memory controller architecture and is coupled to second NVM storing a backup of content of first NVM in the memory controller. With this arrangement, one more memory access path is established, which takes full advantage of the fast reading characteristics of the first NVM, and once a system bus identifies an error in content read from the first NVM or a problematic address, the second memory controller can automatically read exactly corresponding backup content from the second NVM and provide it on the system bus, or use it to accurately correct the error in the first NVM. This ensures correctness of content that a central processing unit (CPU) or other master on the system bus reads, without interrupting execution of the system's program.

Abstract: A memory controller and an MCU chip are disclosed. The memory controller adds a second memory controller to a conventional memory controller architecture and is coupled to second NVM having first and second backup banks. In order to perform an OTA upgrade, one of the first and second backup banks of the second NVM is used as a default backup bank for supporting execution of an ongoing program of the system, and the other as an OTA upgrade backup bank for supporting OTA upgrade control.

Abstract: Disclosed are a memory operating method, memory and electronic device. The memory follows a read-write parallel protocol and includes a plurality of memory banks, and the method comprises: writing data to a specified location of the first memory bank corresponding to a current logical address, and pre-reading original data in a specified location of the second memory bank corresponding to a next logical address in a current clock cycle; encoding the pre-read original data and data to be written next, when an instruction to encode based on the pre-read original data in a next clock cycle is obtained; and writing the encoded data to the specified location of the second memory bank in the next clock cycle. By pre-reading the original data corresponding to the incremental address in the current clock cycle, the present disclosure can accelerate an encoding operation that may occur next.

Abstract: Disclosed are a memory operating method, memory and electronic device. The memory complies with a read-write parallel protocol and includes a plurality of memory banks, and the method includes: sequentially mapping read and write transactions for consecutive logical addresses to different banks according to a predetermined transmission bit width by an address decoder, and arbitrating the read transaction and write transaction mapped to the same bank in a current clock cycle by an arbitration circuit, wherein in case that a specific low address bits of the logical address are the same, the read and/or the write transaction are mapped to the same bank. The disclosure avoids long-term occupation of a certain physical bank with specific low address decoding solution, thereby improving the execution efficiency of the read-write parallel protocol. Furthermore, an arbitration mechanism is introduced to arbitrate read and write conflicts for the same memory bank in each clock cycle.

Abstract: Disclosed are a memory operating method, memory and electronic device. The memory follows a read-write parallel protocol and includes a plurality of memory banks, and the method comprises: writing data to a specified location of the first memory bank corresponding to a current logical address, and pre-reading original data in a specified location of the second memory bank corresponding to a next logical address in a current clock cycle; encoding the pre-read original data and data to be written next, when an instruction to encode based on the pre-read original data in a next clock cycle is obtained; and writing the encoded data to the specified location of the second memory bank in the next clock cycle. By pre-reading the original data corresponding to the incremental address in the current clock cycle, the present disclosure can accelerate an encoding operation that may occur next.

Abstract: Disclosed are a memory operating method, memory and electronic device. The memory complies with a read-write parallel protocol and includes a plurality of memory banks, and the method includes: sequentially mapping read and write transactions for consecutive logical addresses to different banks according to a predetermined transmission bit width by an address decoder, and arbitrating the read transaction and write transaction mapped to the same bank in a current clock cycle by an arbitration circuit, wherein in case that a specific low address bits of the logical address are the same, the read and/or the write transaction are mapped to the same bank. The disclosure avoids long-term occupation of a certain physical bank with specific low address decoding solution, thereby improving the execution efficiency of the read-write parallel protocol. Furthermore, an arbitration mechanism is introduced to arbitrate read and write conflicts for the same memory bank in each clock cycle.

Abstract: An information protection method and device based on a plurality of sub-areas for an MCU chip, the MCU chip comprises an instruction bus, a data bus, a flash controller and a user area of a flash memory, the method comprises: determining a preceding sub-area when the instruction bus accesses the user area; entering corresponding preceding sub-area working state; determining the current sub-area when the instruction bus accesses the user area; when the preceding sub-area is inconsistent with the current sub-area, entering the transition state; determining whether the duration of the transition state reaches the preset waiting time; if yes, entering the corresponding current sub-area working state. The information protection method and device prevent the cooperative companies which develop the program together from stealing program from each other.

Abstract: A flash controller and a control method for the flash controller. The flash controller comprises an instruction bus interface, a data bus interface, a configuration register, an erase access filter module, a read/write access filter module and a flash control module. The read/write access filter module is configured to receive control information and determine whether the read/write access is sent to the flash control module or not. The erase access filter module is configured to receive control information and determine whether the erase access is sent to the flash control module or not. The flash control module is configured to complete an access to a flash memory. The present disclosure is used to protect programs from being stolen by a client, and also protect against a situation where companies collaboratively developing a program are able to steal programs from one another.

Abstract: The disclosure discloses a method and a device of information protection for a micro control unit (MCU) chip, the MCU chip comprises an instruction bus, a data bus, a flash controller and a user area of a flash memory; the flash controller is used to divide the user area into a first sub-area and a second sub-area; the method comprising: when the instruction bus accesses the user area, determining, whether the instruction bus accesses the first sub-area; if yes, entering the first sub-area working state; in the first sub-area working state, if the instruction bus accesses the second sub-area, entering the transition state; determining whether the time at transition state reaches a preset waiting time; if yes, entering the second sub-area working state; the disclosure is used to protect program from being stolen by users and prevent the cooperative companies stealing program from each other.

Abstract: A flash controller and a control method for the flash controller. The flash controller comprises an instruction bus interface, a data bus interface, a configuration register, an erase access filter module, a read/write access filter module and a flash control module. The read/write access filter module is configured to receive control information and determine whether the read/write access is sent to the flash control module or not. The erase access filter module is configured to receive control information and determine whether the erase access is sent to the flash control module or not. The flash control module is configured to complete an access to a flash memory. The present disclosure is used to protect programs from being stolen by a client, and also protect against a situation where companies collaboratively developing a program are able to steal programs from one another.

Abstract: The disclosure discloses a method and a device of information protection for a micro control unit (MCU) chip, the MCU chip comprises an instruction bus, a data bus, a flash controller and a user area of a flash memory; the flash controller is used to divide the user area into a first sub-area and a second sub-area; the method comprising: when the instruction bus accesses the user area, determining whether the instruction bus accesses the first sub-area; if yes, entering the first sub-area working state; in the first sub-area working state, if the instruction bus accesses the second sub-area, entering the transition state; determining whether the time at transition state reaches a preset waiting time; if yes, entering the second sub-area working state; the disclosure is used to protect program from being stolen by users and prevent the cooperative companies stealing program from each other.

Abstract: An information protection method and device based on a plurality of sub-areas for an MCU chip, the MCU chip comprises an instruction bus, a data bus, a flash controller and a user area of a flash memory, the method comprises: determining a preceding sub-area when the instruction bus accesses the user area; entering corresponding preceding sub-area working state; determining the current sub-area when the instruction bus accesses the user area; when the preceding sub-area is inconsistent with the current sub-area, entering the transition state; determining whether the duration of the transition state reaches the preset waiting time; if yes, entering the corresponding current sub-area working state. The information protection method and device prevent the cooperative companies which develop the program together from stealing program from each other.

Abstract: An embedded system controller comprises a main chip and a flash memory. The main chip comprises: a bus; a random access memory; and a storage control module which is configured to copy program data to be used to the random access memory from the flash memory, and also configured to read required program data from the random access memory when receiving a read access request from the bus and write program data to be written into the random access memory and the flash memory when receiving a write access request from the bus. The present application can allow the main chip of an embedded system controller to be manufactured using an advanced standard circuit manufacturing process and achieve excellent performance and power consumption.