Abstract: A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage. A voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.

Abstract: An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type digital-to-analog converter (DAC) and at least one second channel type DAC. The integrated circuit further includes a plurality of sample and hold (S/H) circuits, each of the plurality of S/H circuits being coupled with a single DAC of the DAC circuit. A number of the at least one first channel type DAC is different than a number of the at least one second channel type DAC.

Abstract: A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a two-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage, and a voltage selector. The voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.

Abstract: A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage, and a voltage selector. The voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.

Abstract: An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type digital-to-analog converter (DAC) and at least one second channel type DAC. The integrated circuit further includes a plurality of sample and hold (S/H) circuits, each of the plurality of S/H circuits being coupled with a single DAC of the DAC circuit. A number of the at least one first channel type DAC is different than a number of the at least one second channel type DAC.

Abstract: A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage. A voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.

Abstract: An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type DAC and at least one second channel type DAC. The integrated circuit includes a plurality of sample and hold (S/H) circuits. Each of the S/H circuits is coupled with the DAC circuit. The S/H circuits are capable of receiving signals from the DAC circuit and outputting the signals in parallel.

Abstract: A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage. A voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.

Abstract: A method for converting a multi-bit digital value to an analog value. The method includes, in a first conversion cycle, converting a first set of digital bits to a first analog voltage using passive charge-sharing. The method also includes, in a second conversion cycle, converting a second set of digital bits to a second analog voltage added to the first analog voltage using active charge-sharing. The first set of digital bits and the second set of digital bits are different bits of the multi-bit digital value.

Abstract: A device includes a first power supply line carrying a first positive power supply voltage, and a second power supply line carrying a second positive power supply voltage lower than the first positive power supply voltage. The device further includes a protection circuit having a MOS transistor. A diode is coupled to the MOS transistor. The source-to-drain path of the MOS transistor and the diode are serially coupled between the first and the second power supply lines. The diode is forward biased by the first and the second positive power supply voltages.

Abstract: An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type DAC and at least one second channel type DAC. The integrated circuit includes a plurality of sample and hold (S/H) circuits. Each of the S/H circuits is coupled with the DAC circuit. The S/H circuits are capable of receiving signals from the DAC circuit and outputting the signals in parallel.

Abstract: A method for converting a multi-bit digital value to an analog value. The method includes, in a first conversion cycle, converting a first set of digital bits to a first analog voltage using passive charge-sharing. The method also includes, in a second conversion cycle, converting a second set of digital bits to a second analog voltage added to the first analog voltage using active charge-sharing. The first set of digital bits and the second set of digital bits are different bits of the multi-bit digital value.

Abstract: A device includes a first power supply line carrying a first positive power supply voltage, and a second power supply line carrying a second positive power supply voltage lower than the first positive power supply voltage. The device further includes a protection circuit having a MOS transistor. A diode is coupled to the MOS transistor. The source-to-drain path of the MOS transistor and the diode are serially coupled between the first and the second power supply lines. The diode is forward biased by the first and the second positive power supply voltages.

Abstract: An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type DAC and at least one second channel type DAC. The integrated circuit includes a plurality of sample and hold (S/H) circuits. Each of the S/H circuits is coupled with one of the DAC circuit. The S/H circuits are capable of receiving signals from the DAC circuit and outputting the signals in parallel.

Abstract: A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage, and a voltage selector. The voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.

Abstract: A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage. A voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.

Abstract: A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a two-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage, and a voltage selector. The voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.

Abstract: An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type DAC and at least one second channel type DAC. The integrated circuit includes a plurality of sample and hold (S/H) circuits. Each of the S/H circuits is coupled with one of the DAC circuit. The S/H circuits are capable of receiving signals from the DAC circuit and outputting the signals in parallel.

Abstract: A method of testing a reflection-type LCD projector is disclosed. The present invention provides a method of testing the digital-circuit portion of the data drivers of the silicon wafer LCD of the reflection-type LCD projector, and a method of testing the panel pixel area of the silicon wafer LCD display. The present invention can be applied to LCD display panels manufactured by CMOS process and polysilicon thin film transistor process for the benefits of helping to resolve manufacturing issues during the development stage, thereby shortening the required production time schedule, and reducing the production cost.

Abstract: A thin-film transistor liquid-crystal display (TFT LCD) driver includes a shift register, a sample and hold circuit, a group block, and a controller. The shift register provides N graded sample clocks. Video signals are delivered to the group block via the sample and hold circuit through the control of the controller. The group block having n groups of N switches transfers a group of N pixel signals from the sample and hold circuit to the display. The display driver of the invention providing n.times.N output lines by using N processing units by virtue of the output distribution of the group block not only reduces circuit space, but also lowers the power consumption requirements.