Abstract: The invention provides a dynamic latch, comprising an input terminal for inputting a first data; an output terminal for outputting a second data; a clock signal terminal for supplying a clock signal; a data transmission unit for transmitting the first data under control of the clock signal; and a data output unit for converting the first data into the second data. The data transmission unit and the data output unit are sequentially connected in series between the input terminal and the output terminal, and a node is provided between the data transmission unit and the data output unit. The dynamic latch further comprises a data retention unit electrically connected to the node. The retention time of data can be effectively extended, thereby improving data security and accuracy.

Abstract: A chip frequency modulation method and apparatus of a computing device, a hash board, a computing device, and a storage medium are disclosed. The computing device is provided with at least one operational chip, and the operational chip is provided with a plurality of cores. The chip frequency modulation method includes: operating each of the plurality of cores in the operational chip configured with a plurality of frequencies to run at a working frequency, the working frequency being one of the plurality of frequencies; analyzing a computing performance indicator of each of the plurality of cores at the working frequency; and modulating a working frequency of at least one core up or down according to the computing performance indicator, a modulated working frequency being one of the plurality of frequencies.

Abstract: Provided are a cloud computing power allocation method, a user terminal, a cloud computing power platform, and a system. The method includes: generating a computing power request including a computing power demand and account information of a computing power scheduling center; sending the computing power request to a cloud computing power platform, so that the cloud computing power platform sends a configuration instruction to a computing device cluster according to the computing power request, where the configuration instruction is to allocate to the user terminal a target computing device meeting the computing power demand from the computing device cluster and configure based on the account information the target computing device to execute a computing task issued by the computing power scheduling center; and acquiring from the computing power scheduling center computing power information determined according to a computing result from the target computing device, by using the account information.

Abstract: A waste heat utilization system of an immersed liquid cooling heat dissipation device. The immersed liquid cooling heat dissipation device (100) comprises a liquid cooling tank (110). The liquid cooling tank (110) comprises an oil tank inlet (111) and an oil tank outlet (112). The system further comprises a waste heat utilization device (200). The waste heat utilization device (200) comprises a waste heat utilization body (210), a cold oil outlet (220) and a hot oil inlet (230), the cold oil outlet (220) and the hot oil inlet (230) being connected to the waste heat utilization body (210); the cold oil outlet (220) is connected with the oil tank inlet (111); the hot oil inlet (230) is connected to the oil tank outlet (112); the waste heat utilization body (210) is connected to a heat utilization end (300).

Abstract: A series circuit and a computing device include a power supply terminal for providing voltage for a plurality of chips disposed on the computing device; a ground terminal disposed at one end of each of the plurality of chips relative to the power supply terminal; and a first connection line for separately connecting a first predetermined number of chips of the plurality of chips in series, wherein a communication line is connected between adjacent chips of the first predetermined number of chips, a portion of the communication line is connected to a target connection point, which is disposed on the first connection line and adapted to the adjacent chips, via a third connection line, and the voltage at the target connection point is greater than or equal to the minimum voltage required for communication between the adjacent chips.

Abstract: An electronic device, comprising: a housing; working assemblies mounted in the housing, wherein each working assembly comprises a circuit board and a radiator, the circuit board comprising a substrate and a plurality of working chips provided on the substrate; and the working assemblies are detachably mounted within the housing; a control board connected to the circuit board; and a power source configured to supply power to the circuit board.

Abstract: The present application provides a thermoelectric conversion apparatus, an electronic device, and a waste heat recycling system. The thermoelectric conversion apparatus includes: a power generator including a first end face and a second end face opposite to each other; lead terminals, both the first end face and the second end face of the power generator being provided with the lead terminals, wherein in a case where there is a temperature difference between the second end face and the first end face of the power generator, electric potential is generated in the power generator, and electric energy is output through the lead terminals disposed on the second end face and the first end face of the power generator; and a supporter configured to support and fix the power generator.

Abstract: Disclosed are a hardware acceleration apparatus and an acceleration method for neural network computing. The hardware acceleration apparatus comprises a memory module, a parsing module and a plurality of functional modules, wherein the memory module is used for caching data required by neural network computing; the parsing module is used for receiving an instruction sequence that is predetermined according to the size of the memory module and the data required by neural network computing, for parsing the instruction sequence so as to obtain a plurality of types of operation instructions, and for issuing a corresponding type of operation instruction to each functional module; and each functional module is used for executing a corresponding operation of neural network computing in response to the reception of the corresponding type of operation instruction. By using the hardware acceleration apparatus for neural network computing, the universality of the hardware acceleration apparatus can be improved.

Abstract: A method and apparatus for accelerating a convolutional neural network. The method comprises: splitting, according to rows, a weight matrix of a convolutional layer into a plurality of weight segments, and respectively caching the plurality of weight segments to a plurality of calculation units in a calculation unit array (step 301); reading a plurality of input data streams respectively corresponding to the plurality of weight segments, and inputting the plurality of input data streams in parallel into the plurality of calculation units (step 302), wherein the input data streams are formed by means of splicing a plurality of rows of data in an input feature map of the convolutional layer; and within each calculation unit, performing a sliding window operation and a multiply-accumulate computation on the input data streams on the basis of the cached weight segments, so as to obtain an output feature map of the convolutional layer (step 303).

Abstract: A dilated convolution acceleration calculation method and apparatus.

Abstract: An image recognition method and apparatus. The method comprises: obtaining original image data, convolutional neural network configuration parameters, and convolutional neural network operation parameters from a data transfer bus, the original image data comprising M pieces of pixel data, and M being a positive integer (101); and performing convolutional neural network operation on the original image data by a convolutional neural network operation module according to the convolutional neural network configuration parameters and the convolutional neural network operation parameters (102), wherein the convolutional neural network operation module comprises a convolution operation unit, a batch processing operation unit, and an activation operation unit connected in sequence. The method improves the real timeliness of image recognition.

Abstract: An image recognition processing method and apparatus.

Abstract: In one aspect, an operation method based on a neural network: calculating, according to the sizes of a convolution kernel and an original image, a total number of operation cycles and an image matrix corresponding to each operation cycle; for the image matrix, a plurality of operation units concurrently acquiring the image data and performing a product operation on the image data and pre-stored weight data, to obtain intermediate data; summing the intermediate data to obtain an operation result; and compiling statistics on all the operation results to obtain a target operation result. The overall operation speed is increased in a unit time; the data read logic is simplified; and the bandwidth requirement of a single operation unit for data is reduced. A convolution operation of any size can be performed, and the convolution operation efficiency is improved, thereby increasing the image processing speed.

Abstract: A leakage compensation dynamic register, a data operation unit, a chip, a hash board, and a computing apparatus. The leakage compensation dynamic register comprises: an input terminal, an output terminal, a clock signal terminal, and an analog switch unit; a data latch unit for latching the data under control of the clock signal; and an output drive unit for inverting and outputting the data received from the data latch unit, the analog switch unit, the data latch unit, and the output drive unit being sequentially connected in series between the input terminal and the output terminal, and the analog switch unit and the data latch unit having a node therebetween, wherein the leakage compensation dynamic register further comprises a leakage compensation unit electrically connected between the node and the output terminal.

Abstract: A computational heat dissipation structure includes a circuit board including a plurality of heating components; and a radiator provided corresponding to the circuit board; wherein a space between the adjacent heating components is negatively correlated with heat dissipation efficiency of a region where the adjacent heating components are located. Since the space between the adjacent heating components of the disclosure is negatively correlated with the heat dissipation efficiency of the region where the adjacent heating components are located, i.e., the higher the heat dissipation efficiency of the region where the adjacent heating components are located is, the smaller the space between the adjacent heating components in the region will be, the heat dissipation efficiencies corresponding to the heating components are balanced, and load of a fan is reduced.

Abstract: A computational heat dissipation structure includes a circuit board including a plurality of heating components; and a radiator provided corresponding to the circuit board; wherein a space between the adjacent heating components is negatively correlated with heat dissipation efficiency of a region where the adjacent heating components are located. Since the space between the adjacent heating components of the disclosure is negatively correlated with the heat dissipation efficiency of the region where the adjacent heating components are located, i.e., the higher the heat dissipation efficiency of the region where the adjacent heating components are located is, the smaller the space between the adjacent heating components in the region will be, the heat dissipation efficiencies corresponding to the heating components are balanced, and load of a fan is reduced.