Abstract: Functionality for estimating characteristics of an on-chip noise signal can be implemented on a processing module. An on-chip noise signal is determined at an on-chip determination point of a computer chip. The on-chip noise signal is converted to a frequency-varying signal using a voltage-controlled oscillator implemented on the computer chip. The frequency-varying signal is measured at an off-chip measurement point and frequency information is extracted from the frequency-varying signal. The frequency information is converted to a voltage level associated with the on-chip noise signal based on the relationship between an input voltage provided to the voltage-controlled oscillator and an output frequency generated by the voltage-controlled oscillator.

Abstract: Functionality for estimating characteristics of an on-chip noise signal can be implemented on a processing module. An on-chip noise signal is determined at an on-chip determination point of a computer chip. The on-chip noise signal is converted to a frequency-varying signal using a voltage-controlled oscillator implemented on the computer chip. The frequency-varying signal is measured at an off-chip measurement point and frequency information is extracted from the frequency-varying signal. The frequency information is converted to a voltage level associated with the on-chip noise signal based on the relationship between an input voltage provided to the voltage-controlled oscillator and an output frequency generated by the voltage-controlled oscillator.

Abstract: Functionality for estimating characteristics of an on-chip noise signal can be implemented on a processing module. An on-chip noise signal is determined at an on-chip determination point of a computer chip. The on-chip noise signal is converted to a frequency-varying signal using a voltage-controlled oscillator implemented on the computer chip. The frequency-varying signal is measured at an off-chip measurement point and frequency information is extracted from the frequency-varying signal. The frequency information is converted to a voltage level associated with the on-chip noise signal based on the relationship between an input voltage provided to the voltage-controlled oscillator and an output frequency generated by the voltage-controlled oscillator.

Abstract: Method for repairing a communication link failure. In certain embodiments, the method generally includes communicating with another apparatus using an initial number of channels of a plurality of channels of a communication link; selectively coupling a plurality of communication lanes with the plurality of channels of the communication link, wherein, during an initial state, a first lane of the plurality of lanes is coupled with a first channel of the plurality of channels, and wherein the plurality of channels comprises a spare channel; determining whether at least one channel of the plurality of channels is experiencing a failure; and controlling at least one of the multiplexers such that the failed channel is replaced by another channel of the plurality of channels by using the spare channel.

Abstract: Functionality for estimating characteristics of an on-chip noise signal can be implemented on a processing module. An on-chip noise signal is determined at an on-chip determination point of a computer chip. The on-chip noise signal is converted to a frequency-varying signal using a voltage-controlled oscillator implemented on the computer chip. The frequency-varying signal is measured at an off-chip measurement point and frequency information is extracted from the frequency-varying signal. The frequency information is converted to a voltage level associated with the on-chip noise signal based on the relationship between an input voltage provided to the voltage-controlled oscillator and an output frequency generated by the voltage-controlled oscillator.

Abstract: Computer program product and apparatus for repairing a communication link failure. In certain embodiments, the apparatus generally includes a controller configured to initialize the communication link for communication with another apparatus using an initial number of channels of a plurality of channels. The apparatus may also include a plurality of multiplexers configured to selectively couple a plurality of communication lanes with the plurality of channels of the communication link. In certain embodiments, during an initial state, a first lane of the plurality of lanes may be coupled with a first channel of the plurality of channels, and the plurality of channels may include a spare channel. The controller may determine whether at least one channel of the plurality of channels is experiencing a failure and control at least one of the multiplexers such that the failed channel is replaced by another channel of the plurality of channels by using the spare channel.

Abstract: Mechanisms, in a data processing system comprising an input/output subsystem implementing an industry standard optical bus, for handling a failure of an optical channel in an optical bus are provided. The mechanisms detect, by failure detection logic of the input/output (I/O) subsystem, failure of an optical channel of the optical bus. The mechanisms send, by a controller of the I/O subsystem, a control signal to channel routing logic of the I/O subsystem to control a routing of data signals between active bus lanes of the data processing system and optical channels of the optical bus in response to detecting the failure of the optical channel. The mechanisms control, by the channel routing logic, routing of data signals between the active bus lanes and the optical channels so as to remove the failed optical channel from further use and use a spare optical channel instead of the failed optical channel.

Abstract: Computer program product and apparatus for repairing a communication link failure. In certain embodiments, the apparatus generally includes a controller configured to initialize the communication link for communication with another apparatus using an initial number of channels of a plurality of channels. The apparatus may also include a plurality of multiplexers configured to selectively couple a plurality of communication lanes with the plurality of channels of the communication link. In certain embodiments, during an initial state, a first lane of the plurality of lanes may be coupled with a first channel of the plurality of channels, and the plurality of channels may include a spare channel. The controller may determine whether at least one channel of the plurality of channels is experiencing a failure and control at least one of the multiplexers such that the failed channel is replaced by another channel of the plurality of channels by using the spare channel.

Abstract: Method for repairing a communication link failure. In certain embodiments, the method generally includes communicating with another apparatus using an initial number of channels of a plurality of channels of a communication link; selectively coupling a plurality of communication lanes with the plurality of channels of the communication link, wherein, during an initial state, a first lane of the plurality of lanes is coupled with a first channel of the plurality of channels, and wherein the plurality of channels comprises a spare channel; determining whether at least one channel of the plurality of channels is experiencing a failure; and controlling at least one of the multiplexers such that the failed channel is replaced by another channel of the plurality of channels by using the spare channel.

Abstract: Mechanisms, in a data processing system comprising an input/output subsystem implementing an industry standard optical bus, for handling a failure of an optical channel in an optical bus are provided. The mechanisms detect, by failure detection logic of the input/output (I/O) subsystem, failure of an optical channel of the optical bus. The mechanisms send, by a controller of the I/O subsystem, a control signal to channel routing logic of the I/O subsystem to control a routing of data signals between active bus lanes of the data processing system and optical channels of the optical bus in response to detecting the failure of the optical channel. The mechanisms control, by the channel routing logic, routing of data signals between the active bus lanes and the optical channels so as to remove the failed optical channel from further use and use a spare optical channel instead of the failed optical channel.

Abstract: Mechanisms, in a data processing system comprising an input/output subsystem implementing an industry standard optical bus, for handling a failure of an optical channel in an optical bus are provided. The mechanisms detect, by failure detection logic of the input/output (I/O) subsystem, failure of an optical channel of the optical bus. The mechanisms send, by a controller of the I/O subsystem, a control signal to channel routing logic of the I/O subsystem to control a routing of data signals between active bus lanes of the data processing system and optical channels of the optical bus in response to detecting the failure of the optical channel. The mechanisms control, by the channel routing logic, routing of data signals between the active bus lanes and the optical channels so as to remove the failed optical channel from further use and use a spare optical channel instead of the failed optical channel.

Abstract: Mechanisms, in a data processing system comprising an input/output subsystem implementing an industry standard optical bus, for handling a failure of an optical channel in an optical bus are provided. The mechanisms detect, by failure detection logic of the input/output (I/O) subsystem, failure of an optical channel of the optical bus. The mechanisms send, by a controller of the I/O subsystem, a control signal to channel routing logic of the I/O subsystem to control a routing of data signals between active bus lanes of the data processing system and optical channels of the optical bus in response to detecting the failure of the optical channel. The mechanisms control, by the channel routing logic, routing of data signals between the active bus lanes and the optical channels so as to remove the failed optical channel from further use and use a spare optical channel instead of the failed optical channel.

Abstract: A printed circuit board is disclosed. The printed circuit board includes a first signal transmission layer, a via and a second signal transmission layer. The via connects the first signal transmission layer to the second signal transmission layer. The via includes a first region made of a first dielectric material having a first dielectric constant, and a second region made of a second dielectric material having a second dielectric constant lower than the first dielectric constant. The via allows AC Component of an electromagnetic signal to be transmitted from the first signal transmission layer to the second signal transmission layer while blocking any DC component of the electromagnetic signal.

Abstract: An improved electrical connector for connecting bus lines to a card such as a memory card or media card, including a multi-level connector comprising a latching device having a plurality of insertable latch positions that advantageously allows for selectively connecting or isolating an electrical path to an adjoining connector. The connectors of unpopulated DIMM slots are disconnected from the network along with the traces that would normally form a stub with associated undesirable signal reflections that would otherwise disturb the signal transmitted to the receiving end if not properly terminated. The contacts of the edge connector itself are used as a means to selectively connect or disconnect adjacent/downstream cards in a serially cascaded architecture. The burden of the stubs due to unpopulated card slots and the need to place one card at the far end of the network are thus eliminated.

Abstract: Functionality for estimating characteristics of an on-chip noise signal can be implemented on a processing module. An on-chip noise signal is determined at an on-chip determination point of a computer chip. The on-chip noise signal is converted to a frequency-varying signal using a voltage-controlled oscillator implemented on the computer chip. The frequency-varying signal is measured at an off-chip measurement point and frequency information is extracted from the frequency-varying signal. The frequency information is converted to a voltage level associated with the on-chip noise signal based on the relationship between an input voltage provided to the voltage-controlled oscillator and an output frequency generated by the voltage-controlled oscillator.

Abstract: Functionality for estimating characteristics of an on-chip noise signal can be implemented on a processing module. An on-chip noise signal is determined at an on-chip determination point of a computer chip. The on-chip noise signal is converted to a frequency-varying signal using a voltage-controlled oscillator implemented on the computer chip. The frequency-varying signal is measured at an off-chip measurement point and frequency information is extracted from the frequency-varying signal. The frequency information is converted to a voltage level associated with the on-chip noise signal based on the relationship between an input voltage provided to the voltage-controlled oscillator and an output frequency generated by the voltage-controlled oscillator.

Abstract: An improved electrical connector for connecting bus lines to a card such as a memory card or media card, including a multi-level connector comprising a latching device having a plurality of insertable latch positions that advantageously allows for selectively connecting or isolating an electrical path to an adjoining connector. The connectors of unpopulated DIMM slots are disconnected from the network along with the traces that would normally form a stub with associated undesirable signal reflections that would otherwise disturb the signal transmitted to the receiving end if not properly terminated. The contacts of the edge connector itself are used as a means to selectively connect or disconnect adjacent/downstream cards in a serially cascaded architecture. The burden of the stubs due to unpopulated card slots and the need to place one card at the far end of the network are thus eliminated.

Abstract: The present invention is directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a method including capacitively coupling a plating stub to ground so that the resonant frequency caused by the plating stub in a semiconductor package is shifted away from an operational frequency.

Abstract: Embodiments of the present invention are directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A first outer layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A capacitor is used to capacitively couple the plating stub to a ground layer.

Abstract: A technique is provided to increase signal bandwidth of data processing signals by providing a plating stub as a filter using multiple line segments of different widths to filter the reflected high frequency components bouncing from the stub end toward the signal path. This stub-filter shifts the resonance point to a much higher frequency, placing that point of resonance beyond the bandwidth of interest without sacrificing a low frequency loss. Accordingly, there is provided an apparatus comprising a stub filter of a substrate, comprising a multi-segmented stub comprising a plurality of stub portions, where one of the stub portions has a different impedance than another of the stub portions.