Abstract: Computing architecture comprises an off-chip memory, an on-chip cache unit, a prefetching unit, a global scheduler, a transmitting unit, a pre-recombination network, a post-recombination network, a main computing array, a write-back cache unit, a data dependence controller and an auxiliary computing array. The architecture reads data tiles into an on-chip cache in a prefetching mode, and performs computing according to the data tiles; in the computing process of the tiles, a tile exchange network is adopted to recombine a data structure, and a data dependence module is arranged to process a data dependence relationship possibly existing between different tiles. According to the computing architecture, the data utilization rate can be increased, the data processing flexibility is improved, and therefore Cache Miss is reduced, and the memory bandwidth pressure is reduced.

Abstract: Computing architecture comprises an off-chip memory, an on-chip cache unit, a prefetching unit, a global scheduler, a transmitting unit, a pre-recombination network, a post-recombination network, a main computing array, a write-back cache unit, a data dependence controller and an auxiliary computing array. The architecture reads data tiles into an on-chip cache in a prefetching mode, and performs computing according to the data tiles; in the computing process of the tiles, a tile exchange network is adopted to recombine a data structure, and a data dependence module is arranged to process a data dependence relationship possibly existing between different tiles. According to the computing architecture, the data utilization rate can be increased, the data processing flexibility is improved, and therefore Cache Miss is reduced, and the memory bandwidth pressure is reduced.

Abstract: A multifunctional data reorganization network includes a binary switching unit and a recursive shuffle network (RSN), wherein both the binary switching unit and the recursive shuffle network can enable bidirectional transmission of data, and the data reorganization network completes data reorganization by controlling the transmission direction of a signal in the network. The network may serve as a data transfer path between a storage unit and a computation unit to perform multiple data reorganization functions while transferring data, thereby enabling flexible data structure adjustment of non-regular data, and thus improving data transfer efficiency and computational efficiency of non-regular computation.

Abstract: A parallel computing system is provided, including input ports, a first switching network, a computing array, a second switching network and output ports. The first switching network is receiving input data from the input ports, sequencing the input data according to different computing modes of the computing array and outputting sequenced input data; the computing array is performing parallel computation on the sequenced input data and outputting intermediate data; and the second switching network is sequencing the intermediate data according to different output modes and outputting sequenced intermediate data through the output ports. The present disclosure applies the switching networks to the parallel computing system and performs any required sequencing on the input or output data according to the different computing modes and output modes to complete various arithmetic operations through the computing array after the input data are input into the computing array.

Abstract: A parallel computing system is provided, including input ports, a first switching network, a computing array, a second switching network and output ports. The first switching network is receiving input data from the input ports, sequencing the input data according to different computing modes of the computing array and outputting sequenced input data; the computing array is performing parallel computation on the sequenced input data and outputting intermediate data; and the second switching network is sequencing the intermediate data according to different output modes and outputting sequenced intermediate data through the output ports. The present disclosure applies the switching networks to the parallel computing system and performs any required sequencing on the input or output data according to the different computing modes and output modes to complete various arithmetic operations through the computing array after the input data are input into the computing array.

Abstract: A three-dimensional depth perception apparatus includes a synchronized trigger module, an MIPI receiving/transmitting module, and a multiplexing core computing module, a storage controller module, a memory, and an MUX selecting module. The synchronized trigger module is for generating a synchronized trigger signal transmitted to an image acquiring module; the MIPI receiving/transmitting module is for supporting input/output of the MIPI video streams and other formats of video streams; the multiplexing core computing module is for selecting a monocular structured or a binocular structured light depth perception working mode. The apparatus flexibly adopts a monocular or binocular structured-light depth sensing manner, so as to leverage the advantages of different modes: the MIPI in, MIPI out working manner is nearly transparent to the user, so as to facilitate the user to employ the apparatus, directly obtaining the depth graph.

Abstract: The present invention provides a method of binocular depth perception based on active structured light, adopting a coded pattern projector to project a coded pattern for structured light coding of the projective space or target object (characteristic calibration), then obtaining the coded pattern by means of two cameras on the same baseline and respectively located symmetrically on both sides of the coded pattern projector, after preprocessing and projection shadow detection, estimating the block matching movement in two modes based on the image blocks (binocular block matching and automatic matching) to obtain the offset of the optimal matching block, finally working out the depth value according to the formula for depth calculation and compensating the depth of the projection shadows to generate high-resolution and high-precision depth information.

Abstract: A parallel synchronous scaling engine for multi-view 3D display and a method thereof are provided, wherein selection and combination calculation are provided to an interpolation pixel window, then interpolation calculation is provided to a combined interpolation pixel window of a combined view field, calculation results are directly displayed on a display terminal. That is to say, interpolation is originally provided before stereoscopic pixel rearrangement, which is now improved, in such a manner that screening and combination of pixel points is provided before interpolation calculation. According to the present invention, computation and memory resource is greatly saved. The method is suitable to be implemented by hardware, for satisfying various numbers of viewpoints and interpolation algorithm, and being compatible with multi-view 3D display with the integrated and floating-point pixel arrangement, wherein the computation resource does not need to be increased with increasing of the viewpoints.

Abstract: A three-dimensional depth perception apparatus and method, comprising a synchronized trigger module, an MIPI receiving/transmitting module, and a multiplexing core computing module, a storage controller module, a memory, and an MUX selecting module; wherein the synchronized trigger module is for generating a synchronized trigger signal that is transmitted to an image acquiring module; the MIPI receiving/transmitting module is for supporting input/output of the MIPI video streams and other formats of video streams; the multiplexing core computing module is for selecting a monocular structured light depth perception working mode or a binocular structured light depth perception working mode as needed, including a pre-processing module, a block matching disparity computing module, a depth computing module, and a depth post-processing module.

Abstract: The present invention provides a system and method for adaptively compensating distortion caused by video compression, the method first conducts an edge texture detection and block boundary detection to an image, classifies the area where the pixels to be processed is located to determine whether the pixel is located at a ringing artifact prone area or near the block boundary with blocking artifact. Next, according to the area of the pixel to be processed and the degree of distortion, the present invention adaptively compensate the distortion using different filtering strategies, so as to improve image effect of low bit-rate transmission at the display end, so that a real time requirement that playing at a high-definition, and ultra high-definition display is satisfied.

Abstract: Disclosed is a method for edge-directed adaptive image interpolation and a VLSI implementation device thereof. The method comprises: computing gradient magnitude and gradient direction of source image, obtaining edge information by comparing gradient magnitude and local adaptive threshold value, edge direction is vertical direction of the gradient direction; classifying edge direction, and filtering using edge information, so that an image is divided into regular edge region and non-edge region. Regular edge region interpolation is conducted along edge direction, methods of improved bicubic interpolation, parallelogram bicubic interpolation and parallelogram bilinear interpolation based on local gradient information are adopted according to classification of edge information; non-edge region image interpolation is conducted by adopting improved bicubic interpolation method based on local gradient information.

Abstract: A parallel synchronous scaling engine for multi-view 3D display and a method thereof are provided, wherein, selection and combination calculation are provided to an interpolation pixel window, then interpolation calculation is provided to a combined interpolation pixel window of a combined view field, calculation results are directly displayed on a display terminal. That is to say, interpolation is originally provided before stereoscopic pixel rearrangement, which is now improved, in such a manner that screening and combination of pixel points is provided before interpolation calculation. According to the present invention, computation and memory resource is greatly saved. The method is suitable to be implemented by hardware, for satisfying various numbers of viewpoints and interpolation algorithm, and being compatible with multi-view 3D display with the integrated and floating-point pixel arrangement, wherein the computation resource does not need to be increased with increasing of the viewpoints.

Abstract: The present invention provides a system and method for adaptively compensating distortion caused by video compression, the method first conducts an edge texture detection and block boundary detection to an image, classifies the area where the pixels to be processed is located to determine whether the pixel is located at a ringing artifact prone area or near the block boundary with blocking artifact. Next, according to the area of the pixel to be processed and the degree of distortion, the present invention adaptively compensate the distortion using different filtering strategies, so as to improve image effect of low bit-rate transmission at the display end, so that a real time requirement that playing at a high-definition, and ultra high-definition display is satisfied.

Abstract: Disclosed is a method for edge-directed adaptive image interpolation and a VLSI implementation device thereof. The method comprises: computing gradient magnitude and gradient direction of source image, obtaining edge information by comparing gradient magnitude and local adaptive threshold value, edge direction is vertical direction of the gradient direction; classifying edge direction, and filtering using edge information, so that an image is divided into regular edge region and non-edge region. Regular edge region interpolation is conducted along edge direction, methods of improved bicubic interpolation, parallelogram bicubic interpolation and parallelogram bilinear interpolation based on local gradient information are adopted according to classification of edge information; non-edge region image interpolation is conducted by adopting improved bicubic interpolation method based on local gradient information.

Abstract: The present invention provides a method of binocular depth perception based on active structured light, adopting a coded pattern projector to project a coded pattern for structured light coding of the projective space or target object (characteristic calibration), then obtaining the coded pattern by means of two cameras on the same baseline and respectively located symmetrically on both sides of the coded pattern projector, after preprocessing and projection shadow detection, estimating the block matching movement in two modes based on the image blocks (binocular block matching and automatic matching) to obtain the offset of the optimal matching block, finally working out the depth value according to the formula for depth calculation and compensating the depth of the projection shadows to generate high-resolution and high-precision depth information.